Principal FPGA Design Engineer - FPGA IPs (R48199/rj)

Cadence; San Jose (CA); On-site; USD 170,000 - 190,000; Full time

Job summary

Join a forward-thinking company that is shaping the future of technology! This exciting role focuses on designing and verifying FPGA intellectual properties for the Protium Prototyping Platform. You will be at the forefront of innovation, working on high-end Xilinx FPGAs and utilizing tools like Vivado for simulation and debugging. If you have a Master's in Electrical Engineering and a passion for hardware validation, this is the perfect opportunity to make a significant impact in a dynamic and collaborative environment. Embrace the challenge and be part of a team that values leadership and innovation!

Benefits

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Paid paternity leave

Tuition assistance

Qualifications

• Master's degree in Electrical Engineering with 5+ years of experience.
• Experience with FPGA design and verification using Verilog.

Responsibilities

• Developing FPGA IPs for Protium platform, including design and verification.
• Debugging and fixing internal regression failures for FPGA IPs.

Skills

FPGA Design

Verilog

FPGA Verification

Debugging

Timing Closure

Documentation

Education

Master's degree in Electrical Engineering

Tools

Vivado

Cadence Simulators Incisive

Xcelium

Job description

This range is provided by Cadence. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$170,000.00/yr - $190,000.00/yr

Job Summary

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. This role involves designing, verifying, performing timing closure, and hardware validation of the FPGA IPs.

Key Responsibilities

• Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users;
• Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware;
• Enhancing current IPs as well as developing new IPs;
• Debugging and fixing internal regression failures for FPGA IPs;
• Documenting IPs.

Minimum Qualifications

The ideal candidate will have the following skills and experience:

• Master's degree in Electrical Engineering with 5+ years of experience;
• Experience with FPGA design and verification using Verilog;
• Experience with high-end Xilinx(AMD) FPGAs including using Vivado tool for simulation, place and route;
• Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software;
• Experience using Cadence Simulators Incisive or Xcelium;
• Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI.

Seniority Level

Mid-Senior level

Employment Type

Full-time

Job Function

Engineering and Information Technology

Industries

Computer Hardware Manufacturing

Benefits

• Medical insurance
• Vision insurance
• 401(k)
• Paid maternity leave
• Paid paternity leave
• Tuition assistance