Principal FPGA Design Engineer - FPGA IPs (R44870/rj)

Cadence; San Jose (CA); On-site; USD 170,000 - 190,000; Full time

Job summary

An established industry player is seeking a talented FPGA Engineer to join their innovative team. In this exciting role, you will be responsible for designing and verifying field-programmable gate array (FPGA) intellectual properties for the Protium prototyping platform. You will work closely with design and verification teams to enhance existing IPs and develop new ones, ensuring high-quality documentation and timely releases. This position offers the opportunity to work with cutting-edge technology and contribute to impactful projects in the field of computer hardware manufacturing. If you are passionate about engineering and eager to make a difference, this is the perfect opportunity for you.

Benefits

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Paid paternity leave

Tuition assistance

Qualifications

• Master's degree in Electrical Engineering with 5+ years of experience.
• Expertise in FPGA design and verification using Verilog and Vivado.

Responsibilities

• Develop FPGA IPs for Protium platform, including design and verification.
• Debug and fix internal regression failures for FPGA IPs.

Skills

FPGA Design

Verilog

Timing Closure

Debugging

Documentation

Industry Standard Interfaces

Education

Master's degree in Electrical Engineering

Tools

Vivado

Cadence Simulators (Incisive, Xcelium)

Job description

This range is provided by Cadence. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$170,000.00/yr - $190,000.00/yr

Additional compensation types

Annual Bonus and RSUs

About Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview

Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. With Cadence Protium prototyping platforms, design and verification teams can rapidly bring up a prototype and provide a pre-silicon platform for early software development, system validation, and hardware regressions.

This role is to design, verification, timing closure and hardware validation of the FPGA IPs.

Responsibilities

• Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users;
• Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware;
• Enhancing current IPs as well as developing new IPs.
• Debug and fix internal regression failures for FPGA IPs.
• Documentation of IPs.

Qualifications

The ideal candidate will have the following skills and experience:

• Master degree in Electrical Engineering with 5+ years of experience;
• Experience with FPGA design and verification using Verilog;
• Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route;
• Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software;
• Experience using Cadence Simulators Incisive or Xcelium;
• Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI.

Seniority Level

Mid-Senior level

Employment Type

Full-time

Job Function

Engineering and Information Technology

Industries

Computer Hardware Manufacturing

Benefits

• Medical insurance
• Vision insurance
• 401(k)
• Paid maternity leave
• Paid paternity leave
• Tuition assistance