Principal ASIC/FPGA Verification Engineer [Onsite]

Anysilicon; El Segundo (CA); Hybrid; USD 140,000 - 200,000; Full time

Job summary

RTX in El Segundo, CA seeks a Principal Electrical or Computer Engineer to lead the design, implementation, and verification of advanced testbenches for high‑performance digital ASICs and FPGAs on Mission Systems programs.

You will architect verification environments using SystemVerilog with OVM/UVM, develop RTL testbenches in VHDL/SystemVerilog, and provide technical leadership to project teams, including planning and status reporting. Security clearance and US citizenship are required.

Qualifications

• Bachelor's degree in STEM with 8+ years of experience or advanced degree with 5+ years.
• Active U.S. government security clearance required prior to start.

Responsibilities

• Architect and design verification environments using SystemVerilog with OVM/UVM.
• Create written test plans, test cases, and track code and functional coverage.
• Develop testbenches for RTL block verification using VHDL or SystemVerilog.
• Recommend tools and practices for continuous improvement in ASIC/FPGA verification flow.
• Provide technical leadership for project verification teams, including planning and status reporting.

Skills

RTL verification

SystemVerilog

VHDL

Leadership

Communication

Scripting languages (Python, Perl)

Education

Bachelor's degree in STEM

Advanced degree (MS/PhD)

Tools

QuestaSim

Synplify

Quartus

Vivado

Git

Subversion

Unix/Linux

Job description

Job Description

Join RTX, a leader in aerospace and defense, as a Principal Electrical or Computer Engineer in El Segundo, CA. This role involves leading the design, implementation, and verification of advanced testbenches for high-performance digital ASICs and FPGAs, contributing to critical Mission Systems programs.

Responsibilities

• Architect and design verification environments using SystemVerilog with OVM/UVM.
• Create written test plans, test cases, and track code and functional coverage.
• Develop testbenches for RTL block verification using VHDL or SystemVerilog.
• Recommend tools and practices for continuous improvement in ASIC/FPGA verification flow.
• Provide technical leadership for project verification teams, including planning and status reporting.

Qualifications

• Bachelor's degree in STEM with 8+ years of experience or an Advanced Degree with 5+ years of experience.
• Active U.S. government issued security clearance required prior to start date.
• U.S. citizenship required for security clearance eligibility.
• Experience in developing and simulating RTL designs using VHDL and/or Verilog in a professional environment.
• 4+ years of experience in chip-level verification methodologies.

Skills

• Proficiency in VHDL and/or SystemVerilog for RTL design and verification.
• Experience with revision control systems like Git or Subversion.
• Strong communication skills for collaboration in multidisciplinary teams.
• Familiarity with Unix/Linux environments and scripting languages (C, C++, Python, Perl).
• Knowledge of ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.