Principal Engineer, AI & ML Design Verification (AI2517)

SiMa.ai, Inc.; San Jose (CA); On-site; USD 204,000 - 316,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

SiMa.ai, Inc. in San Jose is seeking a Principal Engineer for AI & ML design verification. You will independently verify MLA components from block to SoC, build test benches, and drive coverage and debugging.

The role requires 12+ years in ML/DSP/CPU/GPU verification, UVM, SystemVerilog, and AMBA knowledge. On-site in San Jose with equity benefits included. The team collaborates with Architecture, SoC Hardware and Software to bring up MLA IP on emulators and silicon, delivering robust

Qualifications

• 12+ years of experience in functional verification of pipeline-based designs.
• Strong UVM and SystemVerilog verification methodology required.
• Experience building UVM test benches from scratch and debugging/coverage tooling.
• Silicon debug on lab/board setup is a plus.
• Knowledge of AMBA protocols is required or strongly preferred.

Responsibilities

• Perform MLA verification execution and closure independently.
• Participate in MLA architecture, micro-architecture and feature reviews.
• Develop MLA test benches using UVM and SystemVerilog.
• Develop and execute test plans and drive code coverage closure.
• Lead debugging of test and regression failures; assist emulation triage.
• Collaborate with Architecture, SoC Hardware and Software teams.

Skills

UVM

SystemVerilog

Debugging

Verification

Education

BS/MS in EE or CS

Tools

BFMs

Scoreboards

SVA

AMBA protocols

Emulation tools

Job description

Job Title: Principal Engineer, AI & ML Design Verification

Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2517

Description: The Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and data processing at block, sub-system and SoC. As well involved in bring-up and debugging on emulators and silicon.

In addition, this job role requires development, enhancement and on-going support and maintenance of MLA Test Bench and Test Cases for SiMa ML IP.

Job Description

As the experienced MLA Design Verification Engineer, you will

• Independently perform MLA verification execution and closure.
• Participate in MLA architecture, micro-architecture and feature discussions and reviews.
• Define and develop MLA test bench components using UVM & System Verilog.
• Develop and execute a test plans.
• Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure.
• Manage debugging of test and regression failures.
• Help emulation team with triaging failures.
• Work closely with the Architecture, SoC Hardware and Software teams.

Required Background

• BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs.
• Very good experience of UVM and System Verilog based verification methodology is a must.
• Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc..) from scratch along with usage know how of debug & coverage tools.
• Skill set for silicon debug on the lab/board set-up is a plus.
• Good debug, coding and problem solving skills.
• Knowledge of AMBA protocols is a must.
• Formal/SVA knowledge is a plus.

Personal attributes

Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

The annual salary for this position ranges from $203,800 - $315,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

EEO Employer

SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.