Principal Engineer, AI & ML Design Verification (AI2517)

SiMa.ai; San Jose (CA); On-site; USD 204,000 - 316,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

SiMa.ai in San Jose, CA is seeking a Principal Engineer, AI & ML Design Verification to lead MLA verification efforts and develop test benches using UVM and SystemVerilog.

Responsibilities include architecture discussions, test plan execution, debugging, and collaboration with architecture, SoC hardware, and software teams. Requires 12+ years in pipeline-based verification and AMBA/SVA knowledge.

Qualifications

• BS/MS in EE or CS with 12+ years of experience in functional verification of pipeline-based designs, preferably MLAs, DSPs, CPUs or GPUs.
• Very good experience of UVM and SystemVerilog verification methodologies.
• Developed UVM/Test Bench components (BFMs, ScoreBoards, SVA) from scratch and proficient with debugging & coverage tools.
• Knowledge of AMBA protocols is a must; SVA knowledge is a plus.

Responsibilities

• Independently perform MLA verification execution and closure.
• Participate in MLA architecture, micro-architecture and feature discussions and reviews.
• Define and develop MLA test bench components using UVM & System Verilog.
• Develop and execute test plans.
• Lead code coverage reviews and closure; SystemVerilog Assertion coverage.
• Manage debugging of test and regression failures.
• Help emulation team with triaging failures.
• Work closely with Architecture, SoC Hardware and Software teams.

Skills

UVM

SystemVerilog

Test Bench Dev

Debugging

AMBA Protocols

SVA

Silicon Debug

Education

BS/MS in EE or CS with 12+ years

Tools

BFMs

ScoreBoards

Debug Tools

Job description

Job Title: Principal Engineer, AI & ML Design Verification

Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2517

Description

The Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and data processing at block, sub-system and SoC. As well involved in bring-up and debugging on emulators and silicon.

In addition, this job role requires development, enhancement and on-going support and maintenance of MLA Test Bench and Test Cases for SiMa ML IP.

Job Description

• Independently perform MLA verification execution and closure.
• Participate in MLA architecture, micro-architecture and feature discussions and reviews.
• Define and develop MLA test bench components using UVM & System Verilog.
• Develop and execute a test plans.
• Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure.
• Manage debugging of test and regression failures.
• Help emulation team with triaging failures.
• Work closely with the Architecture, SoC Hardware and Software teams.

Required Background:

• BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs.
• Very good experience of UVM and System Verilog based verification methodology is a must.
• Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc..) from scratch along with usage know how of debug & coverage tools.
• Skill set for silicon debug on the lab/board set-up is a plus.
• Good debug, coding and problem solving skills.
• Knowledge of AMBA protocols is a must.
• Formal/SVA knowledge is a plus.

Personal Attributes:

Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

The annual salary for this position ranges from $203,800 - $315,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

EEO Employer:

SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.