Principal DV Engineer

Espace; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

Health and wellness care options

Continuous learning and development

Paid holidays

Paid time off

Job summary

Espace in Saratoga is seeking a Digital Design Verification Engineer with over 10 years of experience in the semiconductor industry. Responsibilities include verifying ASICs for satellite and wireless telephony, building UVM verification environments, and debugging simulations.

The role requires expertise in Verilog, SystemVerilog, and proficiency in C/C++ along with strong scripting skills. The position offers competitive salaries and a chance to contribute to innovative space-based communications.

Qualifications

• 10+ years of design verification experience in the semiconductor industry.

Responsibilities

• Verify custom ASICs for satellite and wireless telephony.
• Build UVM verification environments from scratch.
• Write and maintain comprehensive test plans.
• Debug complex RTL simulations.

Skills

Proficient in Verilog

Expert in SystemVerilog

Proficient in C/C++

Strong scripting in Perl or Python

Job description

About E-Space

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, unapologetically curious and 100% committed to innovating space-based communications and delivering actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

Job Overview

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work.

Responsibilities

HDL & Verification Methodology

• Expert-level proficiency in Verilog and SystemVerilog
• Proven experience building UVM verification environments from scratch
• Deep understanding of verification methodologies and best practices

Programming & Scripting

• Proficient in C/C++ coding for verification purposes
• Strong scripting skills in Perl or Python
• Ability to write and maintain bash scripts for verification flows

Verification Planning & Execution

• Experience writing comprehensive test plans
• Experience writing and maintaining test suites
• Ability to debug complex RTL simulations
• Ability to debug gate-level simulations with SDF back‑annotation
• Ability to assess whether SDF timing violations are benign or require attention

Leadership

• Proven track record leading code coverage closure
• Experience leading design verification efforts through chip tapeout

Qualifications

• 10+ years of design verification experience in the semiconductor industry

Employment Details

This is a full‑time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job‑related knowledge, skills, and experience.

E-space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

Why E-space is Right for You

• An opportunity to really make a difference
• Sustainability at our core
• Fair and honest workplace
• Innovative thinking is encouraged
• Competitive salaries
• Continuous learning and development
• Health and wellness care options
• Financial solutions for the future
• Optional legal services (US only)
• Paid holidays
• Paid time off