Principal Design Verification Engineer — Remote Options

Analog Devices; Durham (NC); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Analog Devices, Inc. seeks a highly experienced Principal Design Verification Engineer for its Durham, NC facility. You will lead a small team, define DV strategy and methodologies, and drive verification excellence across power controller products.

The role combines hands-on testing with leadership and cross-functional collaboration. Ideal candidates bring 10+ years in SystemVerilog/UVM verification, formal methods, and a proven track record in mixed-signal SoC verification.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 10+ years of hands-on SystemVerilog/UVM‑based verification.
• 3+ years of technical leadership, mentoring, or managing small teams.
• Experience architecting verification environments for complex mixed-signal SoCs or PMICs.
• Proven DV strategy definition across multiple projects.
• Expert-level EDA tools and automation (Python, TCL, Perl, Shell).
• Experience with formal verification (JasperGold, VC Formal or equivalent).
• Strong coverage-driven verification knowledge and closure strategies.
• Excellent communication for executive-level presentations.

Responsibilities

• Define DV strategy for group aligned with product roadmaps.
• Develop DV plans for multiple projects.
• Drive adoption of advanced DV methodologies including UVM, formal verification, PSS, AI/ML-assisted verification.
• Establish verification metrics, KPIs, and quality gates.
• Lead and mentor a small team of verification engineers.
• Conduct code and testbench architecture reviews and methodology assessments.
• Collaborate on recruiting and onboarding verification talent.
• Architect scalable, reusable verification infrastructure across projects.
• Drive evaluation of new EDA tools and verification IP.
• Lead development of advanced testbench components including UVM environments.
• Support all projects with DV planning and execution oversight.
• Partner with design teams for seamless integration and verification.
• Represent verification in project reviews and executive briefings.
• Develop and document best practices and playbooks for DV organization.
• Stay current with industry trends and drive adoption of innovations.

Skills

SystemVerilog/UVM verification

Technical leadership

DV strategy

Mentoring

Python scripting

Formal verification

UVM environments

C/C++ modeling

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

JasperGold

VC Formal

Cadence

Synopsys

Mentor Graphics

Git

Job description

Analog Devices, Inc. seeks a highly experienced Principal Design Verification Engineer for its Durham, NC facility. You will lead a small team, define DV strategy and methodologies, and drive verification excellence across power controller products.

The role combines hands-on testing with leadership and cross-functional collaboration. Ideal candidates bring 10+ years in SystemVerilog/UVM verification, formal methods, and a proven track record in mixed-signal SoC verification.