Senior AMS Verification Engineer (SystemVerilog/UVM)

Analog Devices, Inc.; Durham (NC); On-site; USD 110,000 - 170,000; Full time

Job summary

Analog Devices, Inc. is seeking a Senior Analog/Mixed-Signal (AMS) Design Verification Engineer to own verification planning and execution for complex mixed-signal ICs.

You will translate specifications into scalable verification architectures, develop reusable SystemVerilog/UVM and real-number models, and drive coverage closure across analog, digital, and mixed-signal interfaces. You will collaborate with analog, digital, firmware, and validation teams to identify risk early, resolve failures,

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 4–8 years of IC verification experience with analog/mixed-signal emphasis.
• Experience delivering verification from planning to post-silicon.
• Proficiency with SystemVerilog real-number modeling, Verilog-AMS, or similar.

Responsibilities

• Verification Strategy and Planning: Own feature-based verification plans, requirements traceability, risk assessment, test strategy, and sign-off criteria for complex AMS IP, subsystems, and SoCs.
• AMS Verification Architecture: Architect scalable, reusable verification environments that combine SystemVerilog/UVM, analog behavioral models, real-number models, and mixed-signal simulation.
• Modeling and Abstraction: Develop and validate behavioral models in SystemVerilog real-number modeling, Verilog-AMS, or equivalent languages to accelerate full-chip verification while maintaining model fidelity.
• Test and Check Development: Create constrained-random and directed tests, scoreboards, reference models, assertions, monitors, and functional coverage for analog-digital interactions, control loops, power modes, calibration, and fault conditions.
• Coverage and Sign-Off: Define measurable code, functional, assertion, and requirements coverage goals; analyze gaps; drive closure; and communicate verification readiness and residual risk.
• Debug and Root-Cause Analysis: Lead cross-domain debug using waveforms, logs, assertions, schematics, and analog measurements to isolate failures involving timing, power sequencing, connectivity, modeling, and design behavior.
• Regression and Automation: Build reliable regression flows, triage infrastructure, dashboards, and automation that improve simulation throughput, reproducibility, and engineering productivity.
• Cross-Functional Execution: Collaborate closely with analog and digital designers, architects, firmware engineers, model developers, and post-silicon validation teams throughout the product lifecycle.
• Technical Leadership: Mentor engineers, lead reviews, establish verification best practices, and influence methodology, tool, and reuse decisions across projects.

Skills

SystemVerilog/UVM

Analog/Mixed-Signal fundamentals

AMS modeling

Mixed-Signal simulation

Verification planning/coverage

Verification techniques

Power-aware verification

Scripting/automation (Python)

Debug/data analysis

Interfaces and system context

Communication/leadership

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree preferred

Job description

Analog Devices, Inc. is seeking a Senior Analog/Mixed-Signal (AMS) Design Verification Engineer to own verification planning and execution for complex mixed-signal ICs.

You will translate specifications into scalable verification architectures, develop reusable SystemVerilog/UVM and real-number models, and drive coverage closure across analog, digital, and mixed-signal interfaces. You will collaborate with analog, digital, firmware, and validation teams to identify risk early, resolve failures,