Staff Design Verification Engineer (SystemVerilog/UVM)

1010 Analog Devices Inc.; Chandler (AZ); Hybrid; USD 172,000 - 199,000; Full time

Benefits offered by this job

Partial telecommute

Job summary

Analog Devices, Inc. in Chandler, AZ seeks a Staff Engineer in Design Verification to define interfaces, verify state machines, and build metric-driven SystemVerilog/UVM environments for data center, energy, and automotive applications.

You will develop directed and constrained random tests, write Verilog-AMS and Real Number Models, and contribute to product definitions while enjoying a partial telecommute option.

Qualifications

• Master’s or Bachelor’s degree with 4–6 years in design verification or related roles.
• Experience with Verilog RTL and function verification.
• Expertise in mixed-signal IC verification techniques and UVM-based test benches.

Responsibilities

• Define and verify interfaces, state machines, and controlling logic for new products.
• Develop targeted random and directed test cases in SystemVerilog.
• Architect and manage metric-driven SystemVerilog/UVM verification environments.

Skills

SystemVerilog

UVM verification

verification environments

test plan development

Python scripting

Perl scripting

C programming

Education

Master's degree in Electrical Engineering

Master's degree in Materials Engineering

Master's degree in Physics

Bachelor's degree in Electrical Engineering

Bachelor's degree in Materials Engineering

Bachelor's degree in Physics

Tools

Cadence AMS

Verilog-AMS

Xcelium

VCS

SystemVerilog

Job description

Analog Devices, Inc. in Chandler, AZ seeks a Staff Engineer in Design Verification to define interfaces, verify state machines, and build metric-driven SystemVerilog/UVM environments for data center, energy, and automotive applications.

You will develop directed and constrained random tests, write Verilog-AMS and Real Number Models, and contribute to product definitions while enjoying a partial telecommute option.