Principal Design Engineer - AI/HP Network IP Architect

Credo; Pittsburgh (Allegheny County); On-site; USD 140,000 - 230,000; Full time

Job summary

Credo is seeking a principal technical leader to drive hands-on digital ASIC design and strategic architectural direction for the High‑Performance Network Interface IP portfolio. The role spans RTL development to shaping product roadmaps and long-range technology investments for AI and HPC systems.

Ideal candidate must have deep expertise in networking, memory subsystems, inter‑chip and intra‑chip interconnects, Ethernet, PCIe, CXL, UCIe, USLink, and related standards.

Qualifications

• Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
• Technical leadership with ability to plan, manage, and influence stakeholders.
• Digital design including state machines, data pathways, FIFOs, asynchronous crossings, high-speed design.
• Verilog/SystemVerilog and synthesizable design concepts targeting deep sub-micron nodes.
• Systems thinking to evaluate tradeoffs and translate into product direction.
• Deep knowledge of networking protocols including Ethernet, PCIe, CXL, UCIe, UALink.
• Experience with inter- and intra-chip buses and NoC, coherent fabrics, latency/bandwidth.
• Understanding of architectural impact on logic synthesis, timing closure, physical implementation.
• Excellent communication for documenting requirements and strategy.
• Unix/Linux scripting (Perl, Tcl, Python, shell).
• Advanced debugging skills.
• FEC algorithm theory and basic data communication theory.
• Experience with Cadence, Mentor, and Synopsys tools for simulation, lint, and synthesis.

Responsibilities

• Lead technical evaluations of RFQs and tradeoffs across power, performance and area.
• Define best-in-class technical solutions with product marketing and customers.
• Help define product and technology roadmaps based on market trends and needs.
• Translate standards and ecosystem trends into architecture goals and priorities.
• Own scoping, planning, and execution tracking of design activities and releases.
• Guide architectural decisions focusing on scalability and impact.
• Create documentation including specs, architecture, microarchitecture, and PRDs.
• Develop, debug RTL; run lint checks and simulation.
• Partner with verification to shape test plans and root-cause analyses.
• Lead design reviews for rigor and quality.
• Perform synthesis: timing constraints, ECOs, and reports analysis.
• Identify risks and drive cross-team mitigation.
• Align engineering, product, and business on customer needs and execution.
• Communicate strategy and priorities to stakeholders.

Skills

Verilog/SystemVerilog

RTL design

Networking protocols

Scripting

Cadence tooling

Education

Electrical/Computer Engineering degree

Tools

Cadence tools

Mentor tools

Synopsys tools

Job description

Credo is seeking a principal technical leader to drive hands-on digital ASIC design and strategic architectural direction for the High‑Performance Network Interface IP portfolio. The role spans RTL development to shaping product roadmaps and long-range technology investments for AI and HPC systems.

Ideal candidate must have deep expertise in networking, memory subsystems, inter‑chip and intra‑chip interconnects, Ethernet, PCIe, CXL, UCIe, USLink, and related standards.