Principal ASIC Verification Engineer

Tara Technical Solutions (TTS); San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Tara Technical Solutions (TTS) in San Jose, CA seeks a Senior Verification Architect to lead the verification strategy for Block/Core/SOC, architect scalable testbenches, and drive coverage with advanced verification methodologies.

Requirements include 12+ years (Bachelor) or 10+ years (Master) in verification, SystemVerilog/UVM/VMM, PCIe knowledge, and full ASIC lifecycle experience. Strong debugging and leadership skills are essential.

Qualifications

• 12+ years of experience with a Bachelor's degree or 10+ years with a Master's in Electrical/Electronics or equivalent.
• 10+ years developing complex verification environments, test plans, functional coverage and pseudo-random testing.
• Full ASIC cycle experience from architecture development to tapeout with a verification focus.
• Proficient in SystemVerilog and verification methodologies like UVM/VMM.
• Strong debugging skills and understanding of complex designs.
• Knowledge of PCIe or similar multi-layered protocols.

Responsibilities

• Architect and develop scalable and reusable Testbench environments.
• Drive test plans for features across Block/Core/SOC and write functional coverage.
• Develop pseudo-random tests to achieve full functional coverage and bring verification to closure.
• Debug regression failures and analyze coverage gaps to improve tests.
• Mentor junior team members and guide verification strategy with design/architecture.
• Lead documentation of verification strategy and lead reviews with design/architecture.
• Improve verification quality and efficiency of the verification process.

Skills

SystemVerilog

UVM/VMM

Functional coverage

Pseudo-random testing

Debugging

Test plan development

Testbench development

Mentoring juniors

PCIe knowledge

Python/Perl scripting

Makefiles

Education

Bachelors in Electrical/Electronics

Masters in Electrical/Electronics

Job description

• Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.
• Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
• Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
• Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
• Work with other members of the team, guide/mentor junior team members
• Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
• Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
• Driver Verification quality and Efficiency improvements

Mandatory Requirements:

• Bachelor's degree in Electrical/Electronics/Equivalent with 12+ years of experience; or Masters degree in Electrical/Electronics/Equivalent with 10+ years of experience
• 10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
• Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification
• Very proficient in System Verilog and Verification Methodologies like UVM/VMM
• Good debug skills in analyzing regression failures and understanding of complex designs
• A good understanding of a complex protocol like PCI Express or other multi-layered protocol

These requirements are a plus:

• Experience in PCIe protocol
• Scripting knowledge of Python or Perl
• Comfort with Makefiles
• Experience with Verifying with other protocols like AXI