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Digitailor is seeking a lead for analog and mixed-signal design to shape next-gen CMOS computing chips at an early-stage AI hardware company in Boston. You will design high-performance blocks and influence chip architecture from concept to tape-out.
Collaborating with IC, systems, physics, and algorithms teams, you will perform layout and verification, test silicon with lab equipment, and help bring probabilistic computing concepts into silicon reality. Hybrid work supported.
Lead analog and mixed-signal design for next-generation CMOS computing chips at an early-stage AI hardware company. You will help shape chip architecture and translate probabilistic computing concepts into practical silicon implementations.
Design analog and mixed-signal blocks, including ADCs, PLLs, bandgaps, regulators, high-speed SerDes, oscillators, and dividers. Own substantial portions of chip architecture and potentially lead the design of an upcoming chip. Perform hands-on layout and design verification, including DRC, ERC, and LVS. Collaborate with IC, systems, physics, and algorithms teams to develop silicon implementations. Contribute to fabricated-chip testing and validation using lab equipment such as signal generators, spectrum analyzers, and oscilloscopes.
6 to 20 years of analog and mixed-signal IC design experience, including work on blocks such as PLLs, ADCs, or SerDes. An MS or PhD in Electrical Engineering focused on circuits or IC design. CMOS circuit design expertise and experience completing multiple tape-outs, including at FinFET or 28nm/65nm nodes. Proficiency with Cadence simulation, including PEX, Monte Carlo, and corner analysis. Hands-on layout experience and familiarity with design verification flows. Experience across multiple circuit types and ability to take on practical tasks beyond a narrow specialty in a startup environment. Compensation & Benefits Base salary range: $200,000 to $325,000 annually. Visa sponsorship is available.
Hybrid, based in Boston, Massachusetts, with three days per week on-site.