Senior Analog/Mixed-Signal Architect (Hybrid—Boston)

Digitailor; Boston (MA); Hybrid; USD 200,000 - 325,000; Full time

Benefits offered by this job

Visa sponsorship available

Job summary

Digitailor is seeking a lead for analog and mixed-signal design to shape next-gen CMOS computing chips at an early-stage AI hardware company in Boston. You will design high-performance blocks and influence chip architecture from concept to tape-out.

Collaborating with IC, systems, physics, and algorithms teams, you will perform layout and verification, test silicon with lab equipment, and help bring probabilistic computing concepts into silicon reality. Hybrid work supported.

Qualifications

• 6–20 years of analog and mixed-signal IC design experience.
• MS or PhD in Electrical Engineering focused on circuits or IC design.
• CMOS circuit design expertise and multiple tape-outs (FinFET/28nm/65nm).
• Cadence simulation proficiency including PEX, Monte Carlo, corner analysis.
• Hands-on layout experience and familiarity with design verification flows (DRC, ERC, LVS).

Responsibilities

• Design analog and mixed-signal blocks (ADCs, PLLs, bandgaps, regulators, high-speed SerDes, oscillators).
• Own substantial portions of chip architecture and potentially lead upcoming chip design.
• Perform layout and design verification (DRC, ERC, LVS).
• Collaborate with IC, systems, physics, and algorithms teams for silicon implementations.
• Contribute to fabricated-chip testing using lab equipment (signal generators, spectrum analyzers, oscilloscopes).

Skills

Analog & mixed-signal design

Layout experience

Design verification

Tape-outs

CMOS circuit design

Education

MS or PhD in Electrical Engineering (circuits/IC design)

Tools

Cadence simulation (PEX, Monte Carlo, corner analysis)

Job description

Digitailor is seeking a lead for analog and mixed-signal design to shape next-gen CMOS computing chips at an early-stage AI hardware company in Boston. You will design high-performance blocks and influence chip architecture from concept to tape-out.

Collaborating with IC, systems, physics, and algorithms teams, you will perform layout and verification, test silicon with lab equipment, and help bring probabilistic computing concepts into silicon reality. Hybrid work supported.