Principal Analog Design Engineer for High-Speed AI Connectivity

Astera Labs; San Jose (CA); On-site; USD 207,000 - 230,000; Full time

Job summary

Astera Labs is seeking a Principal Analog Design Engineer to architect and design high-speed analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O. You will own designs from concept through silicon bring-up, setting the technical bar and mentoring engineers as the team scales.

You will lead designs for PLLs, references, ADCs/DACs, and clocking in advanced CMOS/FinFET nodes, focusing on performance, power, and area. This is a high-impact, hands-on role for an AI connectivity leader.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 8+ years of analog and mixed-signal IC design experience.
• Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
• Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
• Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.

Responsibilities

• Analog & Mixed-Signal Design: Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
• Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.
• Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.
• Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.
• Define and execute test plans to correlate silicon performance against design targets.
• Technical Leadership: Set analog design methodology, review standards, and best practices across the team.
• Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.
• Mentor and guide junior engineers, elevating the technical capability of the analog organization.

Skills

Analog design

Mixed-signal design

High-speed I/O

Cadence tools

Layout/parasitics

Mentoring

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Astera Labs is seeking a Principal Analog Design Engineer to architect and design high-speed analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O. You will own designs from concept through silicon bring-up, setting the technical bar and mentoring engineers as the team scales.

You will lead designs for PLLs, references, ADCs/DACs, and clocking in advanced CMOS/FinFET nodes, focusing on performance, power, and area. This is a high-impact, hands-on role for an AI connectivity leader.