RTL Design Tech Lead - AI Hardware Connectivity

Socket.dev; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs in California is hiring a Tech Lead Design Engineer to architect and deliver connectivity silicon for AI clusters. You will own RTL design from microarchitecture to tapeout and work with architecture, verification, DFT, and physical design teams.

This high-impact role requires 5+ years in digital design, strong Verilog/SystemVerilog skills, and experience with high-speed interfaces. Leadership and mentoring are key, with opportunities to influence tapeout schedules and design

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of digital design experience including at least one full chip from spec to tapeout.
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
• Hands-on timing closure, CDC, lint, and low-power design techniques.
• Solid understanding of PCIe, Ethernet, or similar high-speed interfaces and SoC integration.

Responsibilities

• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
• Drive design reviews, lint, CDC, and timing closure to silicon-ready quality.
• Partner with architecture to translate specifications into implementation-ready microarchitecture.
• Collaborate with verification on testplans, coverage closure, and bug triage.
• Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.
• Mentor junior engineers and contribute to design methodology, scripts, and best practices.

Skills

RTL design

Verilog/SystemVerilog

Timing closure

High-speed interfaces

SoC integration

Debug skills

Technical leadership

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

MS or PhD in Electrical/Computer Engineering

Job description

Astera Labs in California is hiring a Tech Lead Design Engineer to architect and deliver connectivity silicon for AI clusters. You will own RTL design from microarchitecture to tapeout and work with architecture, verification, DFT, and physical design teams.

This high-impact role requires 5+ years in digital design, strong Verilog/SystemVerilog skills, and experience with high-speed interfaces. Leadership and mentoring are key, with opportunities to influence tapeout schedules and design