Senior Digital Design Engineer: AI Connectivity & Security

Asteralabs; San Jose (CA); On-site; USD 135,000 - 195,000; Full time

Benefits offered by this job

Discretionary bonus

Incentives and benefits

Job summary

Astera Labs is seeking a Senior Digital Design Engineer to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. The ideal candidate will work on CPU subsystems and collaborate closely with verification and physical design teams.

Required qualifications include a Bachelor's degree in Electrical Engineering and 3+ years of experience in SoC/silicon products. The base salary range is $135,000 to $195,000, depending on experience and level.

Qualifications

• 3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets.
• Expertise in RTL coding with SystemVerilog and synthesis.
• Experience with CPU subsystem design or embedded processor integration.

Responsibilities

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Contribute to design infrastructure that improves team productivity.

Skills

RTL Design & Implementation

Verification & Quality

Methodology & Automation

Education

Bachelor's degree in Electrical Engineering or equivalent

Tools

SystemVerilog

Python

Synopsys

Cadence

Job description

Astera Labs is seeking a Senior Digital Design Engineer to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. The ideal candidate will work on CPU subsystems and collaborate closely with verification and physical design teams.

Required qualifications include a Bachelor's degree in Electrical Engineering and 3+ years of experience in SoC/silicon products. The base salary range is $135,000 to $195,000, depending on experience and level.