Pre-Silicon Graphics Cache Verification Engineer

Apple Inc.; Santa Clara (CA); Hybrid; USD 150,000 - 278,000; Full time

Job summary

Apple Inc. in Santa Clara, CA, is seeking a Graphics Cache Hierarchy Design Verification Engineer to lead pre-silicon RTL verification of graphics memory subsystems.

The role involves designing verification plans, building test benches, and creating automated verification flows to ensure robust GPU design verification. The successful candidate will have a strong background in computer architecture, SystemVerilog, and verification methodologies, and will collaborate closely with design leads and

Qualifications

• BS in related field and 3+ years of experience.
• Experience in CPU or GPU architecture.
• Experience with SystemVerilog and HDL simulators.

Responsibilities

• Develop verification plans in coordination with design leads and architects.
• Build and maintain portable verification test bench components and environments.
• Generate directed and constrained random tests.
• Run simulations and debug design and environment issues.
• Create functional coverage points, analyze coverage, and improve test environment to target coverage holes.
• Create automated verification flows for block verification.
• Apply knowledge of hardware description languages (VHDL/Verilog) to verify complex designs.
• Work with other block, memory subsystem and core level engineers to ensure seamless verification flow.

Skills

CPU or GPU architecture

Bring-up & debug

SystemVerilog

Education

BS in related field

Tools

HDL simulators

Waveform viewers

UVM

Perl

Ruby

Shell scripting

Makefiles

Job description

Apple Inc. in Santa Clara, CA, is seeking a Graphics Cache Hierarchy Design Verification Engineer to lead pre-silicon RTL verification of graphics memory subsystems.

The role involves designing verification plans, building test benches, and creating automated verification flows to ensure robust GPU design verification. The successful candidate will have a strong background in computer architecture, SystemVerilog, and verification methodologies, and will collaborate closely with design leads and