GPU Physical Verification Engineer: High-Performance Chip Design

Apple Inc.; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Apple Inc. seeks a GPU Physical Verification Design Engineer in Santa Clara, CA.

You will help realize complete physical design verification from planning to tapeout, collaborating with the Physical Design team and cross‑functional partners to ensure robust, power‑efficient GPU implementations. Responsibilities include driving verification methodologies, guidelines, checklists, and resolving design and flow issues related to physical design, with hands‑on work on large chip integration and

Qualifications

• BS + 10 years of relevant experience.
• Experience with hierarchical design, top-down design, budgeting, and physical convergence.
• Experience with Physical Verification checks including Base/Metal DRC, ERC, LVS, Process ANT, PERC, and ESD.
• Experience with P&R flows and Physical Verification tools (e.g. Calibre).

Responsibilities

• Drive physical verification aspects in the design cycle.
• Work with Physical Design team to drive methodologies and best known methods to streamline physical design work, guidelines and checklists.
• Drive execution, track progress and resolve design and flow issues related to physical design.
• Communicate and drive the needs of Physical Design Verification with cross-functional teams to achieve back-end goals.

Skills

Hierarchical design

Top-down design

Physical verification concepts

Cross-functional collaboration

Education

BS degree in Electrical Engineering or related field

Tools

Calibre

Job description

Apple Inc. seeks a GPU Physical Verification Design Engineer in Santa Clara, CA.

You will help realize complete physical design verification from planning to tapeout, collaborating with the Physical Design team and cross‑functional partners to ensure robust, power‑efficient GPU implementations. Responsibilities include driving verification methodologies, guidelines, checklists, and resolving design and flow issues related to physical design, with hands‑on work on large chip integration and