GPU Design Engineer: Memory Hierarchy & Performance

MaziCTools; United States; Remote; USD 143,000 - 264,000; Full time

Job summary

Apple is seeking a GPU Design Engineer in Santa Clara, CA, to contribute to micro-architecture specification and RTL coding for a next-generation GPU memory hierarchy. You will work across verification teams to optimize performance, area, and power, delivering high-quality designs for Apple’s silicon.

A strong background in GPU architecture and HDL is required. BS plus 3+ years of experience, with proficiency in Verilog/SystemVerilog, Python, and scripting, and the ability to collaborate across

Qualifications

• Minimum of 3 years of proven experience and knowledge of CPU or GPU architecture as well as the below:
• Strong background in cache, on-chip interconnect network, data compression or shader processor
• Experience in debugging performance issues.
• Proficiency in high performance, low power designs.
• Proficiency in Verilog/SystemVerilog, HDL
• Experience with scripting languages such as Perl, Python and Ruby is a plus.
• Ability to work well in a team with strong communication skills

Responsibilities

• Participate in micro-architecture specification and RTL coding.
• Explore architecture trade-offs in performance, area and power consumption.
• Collaborate with verification team for functional simulation and debug.
• Demonstrate creativity in problem solving and adapt quickly to new technical areas.

Skills

CPU/GPU architecture

Cache / interconnect

Data compression

GPU design

Debugging performance issues

High performance, low power

Verilog/SystemVerilog

HDL

Python

Perl

Ruby

Education

BS + 3 years experience

Tools

Verilog

SystemVerilog

HDL

Perl

Python

Ruby

Job description

Apple is seeking a GPU Design Engineer in Santa Clara, CA, to contribute to micro-architecture specification and RTL coding for a next-generation GPU memory hierarchy. You will work across verification teams to optimize performance, area, and power, delivering high-quality designs for Apple’s silicon.

A strong background in GPU architecture and HDL is required. BS plus 3+ years of experience, with proficiency in Verilog/SystemVerilog, Python, and scripting, and the ability to collaborate across