GPU Design Verification Engineer — Hybrid Role

Intel Corporation; Santa Clara, Northern (CA, KY); Hybride; USD 164 000 - 232 000; Plein temps

Résumé du poste

Intel Corporation in Santa Clara, CA, is seeking a GPU Design Verification Engineer to perform functional verification of graphics logic components and develop scalable verification plans and test benches. The role involves executing verification plans, running system simulations, and debugging pre-silicon issues while collaborating with GPU architects and RTL teams.

The ideal candidate has a strong background in SystemVerilog/UVM, coverage-driven verification, and scripting skills, with a track

Qualifications

• Minimum degree in electronics or computer engineering with 5+ years of experience or a Master’s with 4+ years.
• Hands-on verification experience for ASIC/CPU/GPU and IP level test bench development.
• Experience with SystemVerilog/UVM, coverage-driven verification, and test plan development.
• Proficiency in scripting languages (Python, Perl) and shell scripting.

Responsabilités

• Perform functional verification of graphics logic components including 3D graphics, media, and display.
• Develop scalable IP verification plans, test benches, and architectures to ensure coverage.
• Execute verification plans, run system simulations, analyze power and timing, and debug.
• Collaborate with GPU architects, RTL, and physical design teams to meet goals.

Connaissances

SystemVerilog

UVM

Test bench bring-up

Python

Shell scripting

Formation

Bachelor’s degree in electronics or computer engineering

Master’s degree in electronics or computer engineering

Outils

Verification tooling

Description du poste

Intel Corporation in Santa Clara, CA, is seeking a GPU Design Verification Engineer to perform functional verification of graphics logic components and develop scalable verification plans and test benches. The role involves executing verification plans, running system simulations, and debugging pre-silicon issues while collaborating with GPU architects and RTL teams.

The ideal candidate has a strong background in SystemVerilog/UVM, coverage-driven verification, and scripting skills, with a track