Power Integrity Co-Design Architect - AI-Driven & Equity

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 136,000 - 265,000; Full time

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Power Integrity Co-Design Engineer to architect di/dt mitigation across silicon, package, board, and platform. This role translates product noise targets into shipped specifications and feeds silicon findings back into the next generation's build.

You will partner with architecture, silicon, and platform teams to define targets, drive closure, and own Sim-to-Si correlation for noise.

Qualifications

• BS/MS/PhD in EE, CE, or related field (or equivalent experience).
• 5+ years in silicon power integrity, voltage noise, or PDN.
• Deep expertise in at least one: di/dt analysis, voltage droop, PDN design, transient noise, decap budgeting, or regulator response.
• Hands-on silicon bring-up, characterization, and correlation.
• Comfort with bench equipment and simulators.
• Strong Sim-to-Si correlation instincts and system-level objectivity.
• Ability to drive decisions in a matrix environment and document outcomes.
• Spec-driven, with documentation and shipment focus.

Responsibilities

• Architect voltage-noise mitigation across silicon, package, board, platform and own codesign trade-offs.
• Co-design noise features with Speed, Power, Reliability, Circuit Design, Power-Arch, ASIC, and platform teams.
• Be the connective tissue across the codesign web.
• Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
• Build and own the Sim-to-Si correlation methodology for noise.
• Model and prototype next-gen noise features and codify them for future programs.
• Lead show-stopper noise bugs during bringup and drive timely resolutions.
• Drive architecture-level codesign tradeoffs across V/F, Power, Noise, Reliability, and Thermal boundaries.

Skills

di/dt analysis

voltage droop

PDN design

silicon bring-up

system-level thinking

Education

BS / MS / PhD in EE/CE or related field

Tools

Oscilloscopes

DAQ systems

Simulators

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Power Integrity Co-Design Engineer to architect di/dt mitigation across silicon, package, board, and platform. This role translates product noise targets into shipped specifications and feeds silicon findings back into the next generation's build.

You will partner with architecture, silicon, and platform teams to define targets, drive closure, and own Sim-to-Si correlation for noise.