Post sillicon validation engineer

Tessolve; San Jose (CA); On-site; USD 90,000 - 150,000; Full time

Job summary

An established industry player in semiconductor engineering is seeking a Post Silicon Validation Engineer to join their dynamic team in San Jose. This role is pivotal in developing and executing end-to-end validation test plans for high-speed SoCs, ensuring quality and performance. With a focus on collaboration across software and hardware teams, you will lead projects from pre-silicon planning to validation sign-off. If you have a passion for innovation and a strong background in silicon validation and embedded systems, this opportunity offers a chance to make a significant impact in a rapidly advancing field. Join us to drive future design improvements and support cutting-edge technology.

Qualifications

• 7+ years in high speed SoC debugging and validation.
• Proficient in programming languages C, C++, Python, and TCL.

Responsibilities

• Develop E2E system validation test plans for SoCs.
• Collaborate with SW and HW teams for test development.

Skills

Debugging high speed SoCs

Silicon validation planning

Embedded software programming

C programming

C++ programming

Python programming

TCL programming

Shell scripting

Protocol knowledge (I2/I3C, SPI, UART, JTAG, PCIe)

FPGA programming

High Speed SerDes testing

TCP/IP knowledge

Automation framework development

Tools

High speed oscilloscopes

Logical analyzers

Job description

Direct message the job poster from Tessolve

Sr. Executive – Talent Acquisition at Tessolve (Hiring VLSI Talents, please reach to [e-mail])

Job Title: Post Silicon Validation Engineer

Location: San Jose, CA

Company: Tessolve

About Tessolve:

Tessolve is a leading provider of engineering and R&D services for semiconductor companies, supporting the full lifecycle from design to testing. With deep expertise in IC design, test engineering, and PCB design, we partner with industry leaders to develop innovative solutions that meet today’s rapidly advancing technological demands.

Mission: Leverage industry experience to lay the groundwork for creating a silicon validation and characterization platform with a strong focus on quality to provide the best possible devices to the datacenter and help drive future design improvements.

Responsibilities & Outcomes:

1. Responsible for developing an E2E system validation test plan for the SoC including characterization.
2. Collaborate with the SW teams to develop a complete suite of tests that enable maximum system level coverage for validation and characterization.
3. Collaborate with the HW teams to develop the optimum solution for test validation and characterization.
4. Responsible for understanding the SoC design to collaboratively work with cross functional teams to create, modify, edit tests and suggest coverage improvements.
5. Responsible for supporting correlation between system and other key platforms to enable a robust production plan.

Ideal Candidates Have/Are:

1. 7+ years of experience in bring up and debug of high speed and high power SoCs.
2. 7+ years of experience in silicon validation planning and leading a project from pre silicon planning, bring up, full SoC validation, and characterization to providing validation signoff before HVM.
3. Comprehensive knowledge of Embedded software programming.
4. Proficient in programming languages such as C, C++, Python, TCL, and Shell scripts.
5. Strong protocol knowledge in I2/I3C, SPI, UART, JTAG, and PCIe.
6. Strong understanding of FPGA programming.
7. Proficient in High Speed SerDes testing.
8. Proficient in TCP IP, UDP, IPv4, IPv6 addressing, Ethernet, DHCP, and DNS.
9. Hands on experience with high speed oscilloscopes and debugging embedded systems using logical analyzers.
10. Basic understanding of how LLMs work.
11. Some experience with DFT (Design For Test).
12. Experience in automation framework development using Python or any other language.
13. Good knowledge of ASIC design flow and silicon FW development process.
14. Flexible to adapt to a very dynamic environment and always carrying forward key improvements.

Seniority Level:

Mid-Senior level

Employment Type:

Contract

Job Function:

Semiconductor Manufacturing