TPU Silicon System Integration and Validation Engineer

Google; Sunnyvale (CA); On-site; USD 132,000 - 189,000; Full time

Job summary

Join a leading technology company as a TPU Silicon System Integration and Validation Engineer, where you'll push the boundaries of chip development and hardware/software integration. Your expertise will contribute to the innovation behind products that impact billions globally. Collaborate with cross-functional teams to ensure the performance and functionality of cutting-edge silicon solutions. This role offers a competitive salary, bonus, and equity, along with a commitment to diversity and inclusion.

Qualifications

• 2 years of experience with industry-standard tools, languages, and methodologies.
• Experience in HW/SW integration and validation.
• Experience with RTL development or evaluation.

Responsibilities

• Review chip specs and coordinate HW/SW integration.
• Drive debug discussions with Design, DV, SW, and Architecture teams.
• Analyze ML workload performance pre/post-silicon.

Skills

Problem Solving

Mentoring

Computer Architecture

ASIC Design

Debugging

Scripting

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Verilog

C++

Python

Job description

TPU Silicon System Integration and Validation Engineer

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Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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info_outline X Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Madison, WI, USA; Sunnyvale, CA, USA.

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering or Computer Science or related field.
• 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
• Experience in HW/SW integration and validation.
• Experience with RTL development or evaluation.
• Experience in the following areas: computer architecture, compilers, computer arithmetic, ASIC design.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 3 years of experience working on FPGA, emulation, or silicon HW environments.
• 2 years of experience working with RTL Simulation OR Emulation/FPGA technologies.
• Experience writing or debugging Verilog / RTL code for ASIC or FPGA designs, waveform debug skills, and knowledge of chip design flows.
• Experience in SW development in C or C++, scripting in Python or similar, and embedded Firmware development.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work on ASIC development, validation, software, tools, and methodologies, with the ability to push the boundaries of chip development and hardware/software integration and validation.

You will contribute to cross-functional work streams focused on Hardware/Software (HW/SW) integration and validation to demonstrate HW, SW, and system functionality and performance. Assist the chip team in meeting silicon development criteria, schedules, and readiness for production in various silicon and system validation environments. Serve as a bridge between specification, design, and verification teams, as well as compiler and performance teams, with technical breadth across Machine Learning compute IP.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud, impacting billions of users globally.

We prioritize security, efficiency, and reliability, from developing TPUs to running a global network, shaping the future of hyperscale computing. Our impact includes Google Cloud’s Vertex AI and Gemini models. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Salary ranges depend on role, level, and location, with individual pay influenced by skills, experience, and education. Your recruiter can provide specific details during hiring.

Responsibilities

• Review chip specs, plan HW/SW integration, coordinate delivery, and benchmark performance with system partners. Enable ML compute features through compiler stack and ML workloads. Integrate and validate hardware and software designs pre-silicon.
• Craft HW-SW co-simulation using RTL, emulation, FPGA, and architectural models for performance correlation.
• Drive debug discussions with Design, DV, SW, and Architecture teams. Root-cause functional failures and performance issues during product development. Improve validation coverage and sign-off processes for quality tapeout and production.
• Plan and design validation tests and microbenchmarks to validate IP functionality and performance. Develop detailed test plans based on design specifications, coordinated with cross-functional teams.
• Analyze ML workload performance pre/post-silicon, contributing to compiler and next-gen chip development.

Google is an equal opportunity employer committed to diversity and inclusion. We value a workforce that reflects our users and fosters a culture of belonging. We prohibit discrimination and harassment based on protected characteristics and encourage all qualified candidates to apply.

English proficiency is required for all roles to facilitate global collaboration. Google does not accept agency resumes; please do not forward resumes to our job postings or employees. We are not responsible for fees related to unsolicited resumes.