Summer EDA Application Engineer Intern – Silicon Design

Cadence

San Jose (CA)

On-site

USD 40,000 - 73,000

Full time

4 days ago

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Benefits offered by this job

401(k) plan with employer match

Paid holidays

Job summary

Cadence offers a three-month summer 2027 internship in San Jose, CA, within the Customer Success Team. You will work with leading EDA tools and experts on silicon design, digital/analog IC design, and AI-enabled design flows.

The program emphasizes hands-on training, cross-team collaboration, and exposure to hardware emulation and design services. The cohort-based program runs summer 2027 with mentors and engineers guiding you through multiple design domains and real-world projects, preparing

Qualifications

Rising senior pursuing a bachelor’s degree in electrical engineering, computer engineering, or another STEM discipline.
Experience with electronic design automation (EDA), foundational silicon, package or board design, or AI use cases is preferred.
Candidates must be able to manage multiple complex assignments and demonstrate strong communication, presentation, assessment, and analytical skills.

Responsibilities

Three-month cohort-based internship program with hands-on training across system and package design; IC design and simulation; physical design and analog layout; verification; hardware emulation; and AI applications.
Learn from technical experts and application engineers who support Cadence’s customers.