Physical Design Lead, TPU, ASIC

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC in Sunnyvale, CA seeks an experienced hardware design leader to drive the physical design of high-performance subchips for AI hardware accelerators. You will oversee RTL to GDSII, timing closures, and power integrity for cutting-edge TPU technology.

You will collaborate with RTL, DFT, packaging teams and external vendors, guide execution schedules, manage risks, and articulate complex technical challenges to stakeholders. Equity and a competitive package accompany the role.

Qualifications

• 10 years of experience in physical design, leading full-chip or sub-chip implementation.
• Experience with RTL2GDSII flow and timing closure for high-speed ASICs.
• Strong scripting in Python, Tcl, or Perl.
• Knowledge of foundry tech files, rule decks, and sign-off processes.
• Ability to communicate complex technical challenges to stakeholders.

Responsibilities

• Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
• Manage the full design cycle from RTL to GDSII, including timing, electrical performance, and power integrity sign-offs.
• Partner with internal teams (RTL, DFT, methodology, packaging) to optimize power, performance, and area (PPA), and conduct feasibility studies for new microarchitectures.
• Collaborate with external EDA and IP vendors to improve flows and methodologies, and contribute to internal processes for efficient execution.
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling leadership across the project.

Skills

Technical leadership

Leadership & communication

PPA trade-offs

DFT (Scan/MBIST/LBIST)

Education

Bachelor's degree in EE/CE/CS

Advanced degree in EE/CE/CS

Tools

Cadence Innovus

Synopsys DP

Mentor Calibre

StarRC

Job description

corporate_fare Google place Sunnyvale, CA, USA

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
  
• Experience in Python, Tcl, or Perl scripting.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, and understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
• Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
  
• Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
• Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will work and provide technical leadership for the physical design of critical sub-chips on our next-generation AI silicon.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google’s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google .

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google’s most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s TPU. You’ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will work and provide technical leadership for the physical design of critical sub-chips on our next-generation AI silicon.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google’s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google .

• Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
  
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
  
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
  
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
  
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
  

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google’s EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.