TPU RTL Design Engineer, Networking, Inter-Chip Interconnects

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google Inc. in Sunnyvale, CA is seeking a Share TPU RTL Design Engineer focused on inter-chip interconnects and AI hardware acceleration. You will design RTL IP for high-speed interconnect subsystems and contribute to TPU architecture and its integration in AI systems.

The role involves project definition, RTL design, verification, and collaboration with multiple teams to deliver data-center accelerators powering Google's AI workloads.

Qualifications

• 4 years of experience in high-performance ASIC design.
• Experience architecting or designing RTL solutions for digital systems.
• Experience developing networking IP across MAC, L2, or PHY layers.
• Experience with high-speed interconnects.
• Preferred: Master’s or PhD focusing on computer architecture.

Responsibilities

• Verify complex digital designs with focus on TPU architecture and integration.
• Design RTL IP for chip-to-chip high-speed interconnect subsystems.
• Participate in project definition, RTL design, and implementation.
• Collaborate with Verification and Physical Design teams to meet timing, area, and power targets.
• Contribute to data center accelerator development and AI hardware.

Skills

RTL design

ASIC design

Networking IP

Interconnects

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Engineering or Computer Science with emphasis on computer architecture

Tools

SystemVerilog

Job description

Share TPU RTL Design Engineer, Networking, Inter-Chip Interconnects

corporate_fare Google place Sunnyvale, CA, USA

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in high-performance ASIC design.
• Experience architecting or designing RTL solutions for digital systems.
• Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers.
• Experience with high-speed interconnects.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 7 years of experience in high-performance ASIC design.
• Experience with IEEE networking standards and applications.

Experience with scripting languages (e.g., Tcl, Python or Perl).

• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
• Familiarity with one or more industry-standard tools for CDC, RDC, RTL Linting, or LEC.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.

As a member of the inter-chip interconnect team, you will play an important role in designing ASIC/SoC hardware for AI and networking accelerators that drive the computational workloads behind Google's most important products. Our hardware accelerators power nearly every product Google offers. Our primary focus is AI acceleration.

You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will have the opportunity to solve challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.

As a member of the inter-chip interconnect team, you will play an important role in designing ASIC/SoC hardware for AI and networking accelerators that drive the computational workloads behind Google's most important products. Our hardware accelerators power nearly every product Google offers. Our primary focus is AI acceleration.

You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will have the opportunity to solve challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Define and document the microarchitecture for complex digital designs within the TPU.
• Write high-quality, performant, and power-efficient RTL code, primarily in SystemVerilog.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.