Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Austin (TX); Sur place; USD 110 000 - 150 000; Plein temps

Résumé du poste

SPACE EXPLORATION TECHNOLOGIES CORP in Austin, TX is seeking a Sr. SOC/ASIC Physical Design Engineer to work on next-generation silicon for space and ground infrastructures. The ideal candidate should have 5+ years of experience in ASIC and physical design flow development along with a Bachelor’s degree in a relevant field.

In this role, you'll collaborate with cross-disciplinary teams and focus on developing innovative solutions that enhance the Starlink network's performance and capabilities.

Qualifications

• 5+ years of ASIC and/or physical design flow development experience in industry.
• Ability to work extended hours and weekends as needed.

Responsabilités

• Perform partition synthesis and physical implementation steps.
• Develop and improve physical design methodologies and automation scripts.
• Collaborate closely with the ASIC design team.
• Resolve design, timing, congestion, and flow issues.
• Run, debug, and fix sign-off closure issues.

Connaissances

ASIC/SOC RTL2GDSII physical design

EDA tools proficiency

Deep sub-micron FinFET and CMOS solid-state physics

CMOS digital design principles

Knowledge of DFT/Scan/MBIST/LBIST

Formation

Bachelor’s degree in electrical engineering

Bachelor’s degree in computer engineering

Bachelor’s degree in computer science

Outils

Industry-standard EDA tools

Description du poste

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Austin, TX

SpaceX was founded under the belief that a future where humanity is exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize its utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation silicon for deployment in space and ground infrastructures around the globe. These chips enable connectivity in places it has previously not been available, affordable, or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g., synthesis, floorplanning, power/ground grid generation, placement and routing, timing, noise, physical verification, electromigration, voltage drop, logic equivalence, and other sign‑off checks).
• Develop and improve physical design methodologies and automation scripts for various implementation steps.
• Collaborate closely with the ASIC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs.
• Resolve design, timing, congestion, and flow issues, identify potential solutions, and drive execution.
• Run, debug, and fix sign‑off closure issues in static timing analysis (STA), noise, logic equivalence, physical verification, electromigration, and voltage drop.

Basic Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of ASIC and/or physical design flow development experience in industry.

Preferred Skills and Experience

• Strong experience in ASIC/SOC RTL2GDSII physical design and sign‑off flows.
• Strong experience with industry‑standard EDA tools, including understanding of their capabilities and underlying algorithms.
• Knowledge of deep sub‑micron FinFET and CMOS solid‑state physics.
• Knowledge of CMOS digital design principles, basic standard cells, their functionality, and standard cell libraries.
• Understanding of CMOS power dissipation in deep sub‑micron processes (leakage/dynamic).
• Familiarity with CMOS analog circuit and physical design.
• Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows.
• Self‑driven individual with a can‑do attitude, willingness to learn, and ability to work in a dynamic group environment.

Additional Requirements

• Ability to work extended hours and weekends as needed to meet critical project milestones.
• To comply with U.S. Government export regulations, the applicant must be a U.S. citizen or national, lawful permanent resident, refugee, asylee, or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence, and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability, or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s affirmative‑action plan or requiring reasonable accommodations for the application/interview process should contact [e-mail].

All application information beyond the scope of this job description, including forms, applications, and voluntary self‑identification, is not included here.