Physical Design - Austin

Qualcomm; Austin (TX); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Competitive annual discretionary bonus

Annual RSU grants

Comprehensive benefits package

Job summary

An established industry player is seeking a skilled Physical Design Engineer to join their innovative team. In this role, you will leverage your expertise in ASIC design and physical verification to develop and implement cutting-edge chips and cores. You will be responsible for the complete Physical Design Flow, ensuring high-speed, low-power designs meet performance goals. This position offers a unique opportunity to work with state-of-the-art tools and technologies, contributing to the future of communication and data processing. Join a collaborative environment that values innovation and creativity, and make a significant impact on next-generation experiences.

Qualifications

• 4+ years in Physical Design and ASIC design/verification.
• Deep knowledge of scripting languages like Python and PERL/TCL.

Responsibilities

• Innovate and implement chips using state-of-the-art tools.
• Conduct power planning, timing optimization, and debugging.

Skills

Physical Design

Place & Route

Timing Closure

Formal Verification

Power Domain Analysis

Physical Verification

Scripting (Python, PERL/TCL)

Linux/Unix Shell

C Programming

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PTSI

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

The QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer, you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.

You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM, DDR, Modem, Audio. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities in this role involve a good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification. The individual also should have deep knowledge of scripting and software languages including Python, PERL/TCL, Linux/Unix shell, and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

Preferred Qualifications:

• 4+ years industry experience in the following areas:
• Physical Design
• Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
• Timing closure experience in Synopsys PTSI
• Formal verification experience
• Power domain analysis experience
• Physical verification experience

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications, or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Pay range and Other Compensation & Benefits:

$115,600.00 - $173,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.