Physical Design Engineer

ALTEN; California (MO); On-site; USD 90,000 - 130,000; Full time

Job summary

A leading engineering firm located in California, Missouri seeks an experienced candidate skilled in RTL synthesis and Static Timing Analysis. The role demands hands-on knowledge in using Cadence tools. You will be responsible for driving closure on timing violations and developing constraints. Furthermore, familiarity with advanced nodes and the ability to thrive in a fast-paced environment are essential. This position requires onsite work of 5 days a week.

Qualifications

• Strong experience in RTL synthesis using Cadence Genus/Fusion compiler.
• Hands-on expertise in Static Timing Analysis using Tempus.
• Ability to analyze and debug timing violations.

Responsibilities

• Develop SDC constraints and optimize QoR.
• Drive closure on timing violations across synthesis and floorplan stages.
• Work in a fast-paced, execution-driven environment.

Skills

RTL synthesis

Static Timing Analysis

Timing closure

Floorplanning

Advanced nodes (5nm or below)

Tools

Cadence Genus/Fusion

Tempus

Cadence Innovus

Job description

• Strong experience in RTL synthesis using Cadence Genus/Fusion compiler, including SDC constraint development and QoR optimization (timing, area, power)
• Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, MMMC scenarios, OCV, and timing signoff concepts
• Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure
• Experience in block-level floorplanning using Cadence Innovus, or fusion compiler including macro placement, IO planning, utilization,
• Experience in advanced nodes (5nm or below) with ability to work in a fast-paced, execution-driven environment (onsite – 5 days/week mandatory)