Physical Design Engineer in Piscataway

Energy Jobline ZR; Piscataway Township (NJ); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Bonus based on performance

Paid time off

Training & development

Job summary

Energy Jobline ZR in San Jose, CA, is seeking a Physical Design Engineer to drive the full physical design cycle from RTL to tape-out, onsite five days. You will execute synthesis, placement, routing, timing closure, and floorplanning while collaborating with RTL engineers.

Candidates should have a Bachelor's in Electrical/Electronics Engineering, TCL/Perl scripting, and proficiency with EDA tools. Excellent verbal and written communication are essential in this collaborative, fast-paced

Qualifications

• Bachelor's degree in Electrical Engineering or Electronics Engineering.
• Experience in Physical Design, Synthesis, Floorplanning, and P&R.
• Proficiency with TCL/Perl scripting and EDA tools.
• Excellent verbal and written communication skills.

Responsibilities

• Execute Physical Design, Synthesis, Physical Verification, and Timing Closure.
• Setup and Synthesizing RTL.
• Timing closure through various methods and strategies; strong STA experience.
• EM/IR Analysis.
• Place and Route.
• Clock Tree Synthesis; experience with clock trees and skew balancing techniques.
• Floor-planning and Layout; strong floorplanning experience.
• Develop flows and methodologies.
• Collaborate with IC Design RTL Engineers.

Skills

TCL scripting

Perl scripting

Physical design

Strong communication

Education

Bachelor's degree in Electrical Engineering or Electronics Engineering

Tools

EDA tools

Job description

Physical Design Engineer

Location: San Jose CA- 5 Days onsite

What will you do

• Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure
• Setup and Synthesizing RTL
• Timing closure through various methods and strategies; preferable in-depth experience in top-level STA
• EM/IR Analysis,
• Place and Route
• Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew
  balancing techniques
• Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
• Flow and Methodology Development …
• Collaborating with IC Design RTL Engineers

What you will Bring

• TCL/PERL Scripting
• Proficiency in related EDA Tools
• Full physical design cycle experience: RTL to Tape-out
• Excellent verbal and written communication skills

Education and Experience Requirements

• Minimum: Bachelor’s degree required in Electrical Engineering or Electronics
  Engineering

Benefits

• Bonus based on performance
• Paid time off
• Training & development

Job Description

Job Description