Physical Design Engineer — End-to-End Chip Timing

Downtown Boulder Partnership; San Jose (CA); On-site; USD 103,320 - 137,760; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

401k

Critical Illness Insurance

Life Insurance

Accident Insurance

Other Perks

Job summary

LanceSoft, Inc. in San Jose, CA is seeking a Physical Design Engineer to lead end-to-end physical design activities for complex digital designs. The role emphasizes hands-on synthesis, PnR, and timing closure in advanced process nodes, with collaboration across design, packaging, and test teams.

The ideal candidate has 5+ years in physical design, strong experience with Cadence/Synopsys tool flows, and a track record of tapeouts on 7nm and below, including SOC/ASIC/GPU/CPU design contexts.

Qualifications

• 5+ years of experience in Physical Design and timing closure.
• Hands-on experience with synthesis, PnR and STA using Cadence/Synopsys tools.
• Experience in multiple large SoC tapeouts in advanced nodes (7nm and below).

Responsibilities

• Define physical architecture with logic design to drive physical design cycle.
• Collaborate across teams: physical design, logic design, package, DFT and test.
• Hands-on synthesis and PnR for high-speed digital designs in advanced process nodes.
• Perform sign-off including power, timing, physical verification checks, and design closure.

Skills

Physical design

Timing closure

Synthesis

Place & Route (PnR)

STA

Tools

Cadence tools

Synopsys tools

Job description

LanceSoft, Inc. in San Jose, CA is seeking a Physical Design Engineer to lead end-to-end physical design activities for complex digital designs. The role emphasizes hands-on synthesis, PnR, and timing closure in advanced process nodes, with collaboration across design, packaging, and test teams.

The ideal candidate has 5+ years in physical design, strong experience with Cadence/Synopsys tool flows, and a track record of tapeouts on 7nm and below, including SOC/ASIC/GPU/CPU design contexts.