Physical Design Engineer at LanceSoft, Inc. San Jose, CA

Downtown Boulder Partnership; San Jose (CA); On-site; USD 103,320 - 137,760; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

401k

Critical Illness Insurance

Life Insurance

Accident Insurance

Other Perks

Job summary

LanceSoft, Inc. in San Jose, CA is seeking a Physical Design Engineer to lead end-to-end physical design activities for complex digital designs. The role emphasizes hands-on synthesis, PnR, and timing closure in advanced process nodes, with collaboration across design, packaging, and test teams.

The ideal candidate has 5+ years in physical design, strong experience with Cadence/Synopsys tool flows, and a track record of tapeouts on 7nm and below, including SOC/ASIC/GPU/CPU design contexts.

Qualifications

• 5+ years of experience in Physical Design and timing closure.
• Hands-on experience with synthesis, PnR and STA using Cadence/Synopsys tools.
• Experience in multiple large SoC tapeouts in advanced nodes (7nm and below).

Responsibilities

• Define physical architecture with logic design to drive physical design cycle.
• Collaborate across teams: physical design, logic design, package, DFT and test.
• Hands-on synthesis and PnR for high-speed digital designs in advanced process nodes.
• Perform sign-off including power, timing, physical verification checks, and design closure.

Skills

Physical design

Timing closure

Synthesis

Place & Route (PnR)

STA

Tools

Cadence tools

Synopsys tools

Job description

Position Title

Physical Design Engineer job at LanceSoft, Inc., San Jose, CA.

Pay rate range: $75/hr to $100/hr on W2

Job Description

Adding more Info to specs as below-

• Well-rounded technical leads with extensive experience in large sub-systems and full-chip
• Min 2–3 full chip execution with End‑to‑End Physical Design activities like FCT (full chip Timing) and FCFP (full chip floor planning)
• Good communication skills as he will be representing AW in customer discussions at the customer site
• Should be able to handle complex tech questions coming from the customer

Responsibilities

• Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle.
• Collaborate across teams (physical design, logic design, package, DFT and test).
• Hands‑on synthesis and PnR using industry standard tools for high-speed digital designs in advanced process nodes.
• Perform all aspects of sign‑off including power, timing, physical verification checks, and design closure.

Experience

• 5+ years of experience in Physical Design and timing closure.
• Hands‑on experience in synthesis, PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below.
• Must have experience of multiple large SoC tapeouts in advanced nodes including hands‑on experience in chip‑level physical design and STA closure.
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped‑out designs, expertise in timing closure at block/chip levels and ECO flows.

Benefits

• Four options of medical Insurance
• Dental and Vision Insurance
• 401k Contributions
• Critical Illness Insurance
• Voluntary Permanent Life Insurance
• Accident Insurance
• Other Employee Perks

EEO Statement

LanceSoft is a certified Minority Business Enterprise (MBE) and an equal opportunity employer. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws.

This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time.