Physical Design Engineer - 7nm Timing & CTS

HCL Technologies Limited; Palo Alto (CA); Vor Ort; USD 110.000 - 138.000; Vollzeit

Zusammenfassung

HCLTech in Palo Alto is seeking a highly talented Ontology - Physical Design Engineer to advance silicon design through innovation. You will drive floorplanning, power planning, placement, routing, CTS, timing closure, and signoff across advanced nodes, while collaborating with foundry and CAD teams to debug timing, power, and variability issues.

The role offers a pay range of $80 to $100 per hour, with performance-based bonuses and a broad set of benefits.

Qualifikationen

• Exposure to TSMC 2NP/3NP is required.
• Experience with floorplanning, placement, routing, CTS and signoff.
• Ability to diagnose DRC/LVS/ERC issues and optimize timing across corners.
• Collaboration with foundry and CAD teams to resolve complex timing and variability.

Aufgaben

• Drive floorplanning, power planning, placement and routing for advanced nodes.
• Achieve timing closure across modes and corners and manage signoff.
• Resolve DRC, LVS, ERC violations and perform physical verification.
• Collaborate with foundry/CAD teams and drive automation improvements.

Kenntnisse

TSMC 2NP/3NP

Floorplanning

Power planning

Placement & optimization

CTS

Routing

Timing closure

DRC/LVS/ERC/signoff

Physical verification

SI/Crosstalk

IR drop & EM analysis

Advanced nodes (7nm/5nm/3nm)

Automation flows

Jobbeschreibung

HCLTech in Palo Alto is seeking a highly talented Ontology - Physical Design Engineer to advance silicon design through innovation. You will drive floorplanning, power planning, placement, routing, CTS, timing closure, and signoff across advanced nodes, while collaborating with foundry and CAD teams to debug timing, power, and variability issues.

The role offers a pay range of $80 to $100 per hour, with performance-based bonuses and a broad set of benefits.