Physical Design Engineer

Fortell; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Fortell in California is seeking an experienced ASIC Physical Design Engineer to drive chip implementation from synthesis through signoff, partnering with architects, RTL designers, and DFT engineers. You will ensure power-aware convergence, meet strict schedules, and lead verification signoffs across partitions.

This role requires 7+ years in physical design, fluency with Innovus/Tempus/Quantus, and strong TCL scripting to optimize flows and reduce risk across SoC implementations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, CS, or related field.
• 7+ years hands-on experience in physical design, synthesis, PnR, timing convergence and physical verification.
• Proficiency with EDA tools (Innovus, Tempus, Quantus) and deep understanding of physical design flows.

Responsibilities

• Execute synthesis, PNR, and STA for assigned ASIC partitions with tight schedules.
• Collaborate with architects, RTL, and DFT teams to resolve design issues.
• Close EM/IR and drive LEC/physical verification signoff for partitions.
• Partner with design teams to address physical design challenges for efficient convergence.
• Refine implementation methodologies across PnR, EM/IR, PDN and LEC flows.
• Troubleshoot flow issues and coordinate with EDA vendors as needed.

Skills

Synthesis

PnR

Physical verification

Timing convergence

EM/IR

TCL scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field

Tools

Innovus

Tempus

Quantus

Cadence/Synopsys TCL scripting

Job description

Fortell is building breakthrough AI-powered hearing technology that redefines how people experience sound and connect with the world. Powered by custom silicon and advances in hearing science, our hearing aids help people hear, and live, with greater clarity and confidence.

Job Responsibilities

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
• Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
• Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
• Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.

Preferred Qualifications

• 7+ years of experience in physical design roles and related activities.
• Proven ability to adhere to tight schedules and implement low-power design techniques.
• Experience in System-on-Chip (SoC) design and implementation.
• Expertise in sub-7nm node technologies.
• Familiarity with industry-standard EDA tools and their capabilities.
• Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

Compensation Range: $150K - $250K