Physical Design Engineer

Eridu AI; Saratoga (CA); On-site; USD 210,000 - 260,000; Full time

Job summary

Eridu AI, a Silicon Valley hardware startup, is seeking a senior engineer to define the physical assembly of SOCs. This role involves extensive collaboration with multi-functional teams to optimize AI infrastructure performance. Candidates should have a Master's or Bachelor's in Electrical Engineering and over 10 years of relevant experience.

Qualifications

• 10+ years of experience in physical design.
• Familiarity with deep sub-micron technologies 7nm or below.
• Knowledge of Verilog and System Verilog.

Responsibilities

• Define the Physical Assembly of SOC including design functions.
• Work with Micro-architects on performance, power & area tradeoffs.
• Develop physical design methodologies and customize recipes.

Skills

Scripting

Problem Solving

Communication

Organization

Education

Master’s Degree in Electrical Engineering

Bachelor’s Degree in Electrical Engineering

Tools

Synthesis CAD tools

Place & Route tools

Verification CAD tools

Job description

Eridu AI isa Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers.

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens) .

Key Responsibilities:

• Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power.
• Proficiency in Synthesis design constraints (SDC).
• Design and Architect Top Level and block Level Floor planning of the entire SoC.
• Sound Proficiency in either Innovus or Synopsys Fusion Compiler required. Proficiency in synthesis, Floor planning Power Planning and Timing closure are required.
• Prior experience with large skew optimized clock tree designs like H-Tree preferred. Clock Grid exposure is a plus.
• Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
• Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
• Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.

Qualifications

• Master’s Degree or bachelor’s degree in EE with a minimum of 10+ years of experience.
• Knowledge using synthesis, place & route, analysis and verification CAD tools.
• Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
• Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL.
• Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
• Knowledge of Verilog and System Verilog.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.
• Prior experience of multiple tape-out in deep submicron 7nm or below is required.

Why Join Us?

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.

The pay range for this role is:

210,000 - 260,000 USD per year (San Francisco Bay Area)