Physical Design Engineer

AECOM; Cupertino (CA); On-site; USD 143,000 - 215,000; Full time

Job summary

AECOM is seeking a Physical Design Engineer in Cupertino, California. In this role, you'll contribute to high-performance PHY design, ensuring compliance with timing, area, and power constraints. Candidates should have a Master’s degree in Electrical Engineering and experience using tools like Cadence and Synopsys. The position offers competitive compensation and a range of employee benefits.

Benefits

Stock programs

Medical and dental coverage

Retirement benefits

Educational reimbursement

Bonuses

Relocation assistance

Qualifications

• Master’s degree or equivalent in Electrical Engineering.
• Experience with industry standard tools (Cadence, Synopsys).

Responsibilities

• Contribute to the physical design from RTL to GDSII.
• Generate timing constraints and perform place and route.
• Run physical design verification and guide other designers.

Skills

Electrical Engineering

Physical Design tools

Timing constraints

Low-power techniques

Scripting (Tcl, Perl, Python)

Education

Master’s degree in Electrical Engineering

Tools

Cadence

Synopsys

Job description

Physical Design Engineer

Location: Cupertino, California, United States

Department: Hardware

Summary

Posted: Jun 05, 2025

Weekly Hours: 40

Role Number: 200607016

Imagine what you can do here. Apple is a place where extraordinary people gather to do their best work. Together, we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Contribute to all phases of the physical design of high-performance PHY design from RTL to delivery of final GDSII. Generate block/chip level static timing constraints. Build full chip floor plan including pin placement, partitions, and power grid. Develop and validate high-performance, low-power clock network guidelines. Perform block-level place and route and close the design to meet timing, area, and power constraints. Generate and implement ECOs to fix timing, noise, and EM IR violations. Run physical design verification at chip/block level and guide other designers to fix LVS/DRC violations. Participate in establishing CAD and physical design methodologies for correcting construction designs. Assist in flow development for chip integration. This role involves 40 hours/week. The base pay range is $143,100 - $214,500 per year, depending on skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees have opportunities such as stock programs, medical and dental coverage, retirement benefits, discounts, educational reimbursement, bonuses, and relocation assistance. Learn more at Apple Benefits.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field.
• Experience with Cadence or Synopsys Physical Design tools, wire routing, synthesis, timing constraints, LVS/DRC/ERC issues, APR flow, CTS, scripting (Tcl, Perl, Python), timing ECO, low-power techniques, PPA data analysis, electromigration, IR-drop analysis, and layout guidelines.

Preferred Qualifications: N/A

Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics. For more information, see EEO Rights. We also participate in the E-Verify program and provide reasonable accommodations for applicants with disabilities. Apple is a drug-free workplace and considers all qualified applicants, including those with criminal histories, in accordance with applicable laws.