Physical Design Engineer

Danta Technologies; Palo Alto (CA); On-site; USD 94,000 - 127,000; Full time

Job summary

Danta Technologies in Palo Alto seeks a Physical Design Engineer for a long-term onsite role. You will work on advanced nodes and collaborate with RTL, DFT, test engineers, and foundry/CAD teams.

The role covers floorplanning, power and clock planning, placement, CTS, routing, and signoff, with emphasis on timing closure and low-power techniques. Prior TSMC 2NP/3NP exposure is required.

Qualifications

• Exposure to end-to-end physical design flow, including floorplanning, placement, routing, and signoff.
• Experience with timing closure and signoff tools (STA, IR, EM) is required.
• Knowledge of low-power techniques (multi-Vt, UPF, power/clock gating) is preferred.
• Familiarity with 7nm+ nodes and collaboration with RTL/DFT/test and foundry/CAD teams.

Responsibilities

• Perform end-to-end physical design flow: floorplanning, power planning, placement, CTS, routing, and post-route optimization.
• Achieve timing closure across all modes and corners.
• Resolve DRC, LVS, ERC and signoff violations.
• Handle low-power design techniques and UPF implementations.
• Perform physical verification and signoff (STA, SI, Crosstalk, IR drop, EM).
• Collaborate with RTL, micro-architecture, DFT/test, and foundry/CAD teams.

Skills

TSMC 2NP/3NP

Physical design

Floorplanning

Power planning

Placement & routing

CTS

Timing closure

DFT & signoff

UPF / multi-Vt

IR/EM analysis

Job description

Employment Eligibility Statement

Due to specific project and client requirements, this position is open to U.S. Citizens and U.S. Lawful Permanent Residents (Green Card holders). Sponsorship is not available at this time.

Danta Technologies evaluates all candidates in compliance with the Immigration and Nationality Act (INA) and EEOC guidelines. All hiring decisions are made without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, or any other protected characteristic.

Position

Physical Design Engineer

Location: Palo Alto, CA (Onsite position)

Long term position

Pay Rate: $80/hr on W2. Selected candidate will be working under Danta Technologies payroll for this position.

Job Description

• Exposure to TSMC 2NP/3NP is must
• Perform end�?to�?end physical design flow:
  • Floorplanning
  • Power planning (PG grid, IR)
  • Placement & optimization
  • CTS (Clock Tree Synthesis)
  • Routing
  • Post�?route optimization
• Achieve timing closure across all modes and corners
• Resolve DRC, LVS, ERC and signoff violations
• Handle low�?power design techniques:
  • Multi�?Vt, Multi�?voltage (UPF)
  • Power gating, clock gating
• Perform physical verification and signoff:
  • STA (Primetime)
  • SI / Crosstalk
  • IR drop & EM analysis
• Work on advanced nodes (7nm, 5nm, 3nm or below)
• Collaborate with:
  • RTL & Micro�?architecture teams
  • DFT & Test engineers
  • Foundry and CAD teams
• Debug complex timing, congestion, power, and variability issues
• Drive methodology improvements and automation (scripts/flows)

Notes

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Danta offers a compensation package to all W2 employees that are competitive in the industry. It consists of competitive pay, the option to elect healthcare insurance (Dental, Medical, Vision), Major holidays and Paid sick leave as per state law.

The rate/ Salary range is dependent on numerous factors including Qualification, Experience and Location.

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