Senior Engineer, Digital Design (Physical)

Analog Devices; Wilmington (MA); On-site; USD 116,960 - 160,820; Full time

Benefits offered by this job

Medical, Vision and Dental

401k

Paid vacation

holidays

Sick time

Job summary

Analog Devices, Inc. in the United States seeks a Senior Physical Design Engineer to lead improvements to physical design flows across complex chip and SoC programs. This role aims to improve scalability, reuse, efficiency, and predictability of implementation flows while coordinating with multiple functional teams.

You will drive flow development, automation, and guardrail definitions, analyze QoR, and provide technical guidance to ensure robust, repeatable design closures across projects.

Qualifications

• Strong experience in PD flow development and automation.
• Solid foundation in floorplanning, placement, CTS, routing, timing closure.
• Experience with PD tools for implementation, analysis, and debugging.
• Strong Tcl/Python scripting to automate workflows.
• Excellent cross-functional collaboration.
• Systematic problem solving.

Responsibilities

• Lead improvements to physical design methodology.
• Develop, refine, and maintain PD flows and automation.
• Define guardrails and repeatable flow practices.
• Analyze QoR to identify gaps and drive improvements.
• Partner with cross-functional teams to translate needs.
• Investigate and resolve convergence issues.
• Provide technical guidance on methodology usage.
• Support implementation validation and troubleshooting.

Skills

Physical design flows

Automation scripting

PD fundamentals

Clock tree synthesis

Placement and routing

Tcl/Python scripting

Cross-functional collaboration

Problem solving

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree or PhD

Tools

Synopsys PD tools

Cadence tools

Job description

Senior Physical Design Engineer

Analog Devices, Inc. (NASDAQ: ADI) seeks a Senior Physical Design Engineer to lead methodology improvements for physical design across complex chip and SoC programs. This role focuses on improving scalability, reuse, efficiency, and predictability of physical implementation flows across teams and projects. The individual will work closely with physical design, CAD, STA, DFT, and design teams to identify gaps and drive flow improvements.

Key Responsibilities

• Methodology Leadership: Drive improvements to physical design methodology, with a focus on flow standardization, reuse, execution efficiency, and more predictable design closure.
• Flow Development and Automation: Own development, refinement, and maintenance of physical design flows, scripts, and automation that reduce manual effort and improve execution quality.
• Best Practice Definition: Define and document physical design guardrails, recommended methodologies, and repeatable flow practices for use across teams and programs.
• QoR and Flow Analysis: Analyze power, performance, area, timing, and congestion outcomes to identify methodology gaps and recurring flow limitations and drive durable improvements.
• Cross‑Functional Enablement: Partner with physical design, CAD, STA, DFT, RTL, and project stakeholders to translate program needs into practical methodology improvements and support broader adoption.
• Debug and Root Cause Resolution: Investigate recurring implementation and convergence issues, identify underlying flow or design contributors, and implement robust corrective actions.
• Technical Guidance: Provide guidance to engineers on methodology usage, flow adoption, debugging strategies, and physical design best practices that improve consistency across projects.
• Implementation Support: Provide targeted implementation support as needed to validate methodology changes, troubleshoot critical flow issues, and ensure improvements are grounded in real project needs.

Must Have Skills

• Strong experience developing and improving physical design flows, automation, and reusable implementation methods.
• Solid background in digital physical design fundamentals, including floorplanning, placement, clock tree synthesis, routing, optimization, and timing closure.
• Experience with industry‑standard physical design and signoff tools for implementation, analysis, and debug.
• Strong scripting skills (Tcl, Python, etc.) to automate workflows and scale methodology improvements.
• Systematic problem‑solving ability to analyze recurring issues and translate findings into durable improvements.
• Excellent cross‑functional communication and teamwork across physical design, CAD, verification, and project teams.
• Strong technical judgment to balance methodology quality, schedule, and implementation constraints.

Preferred Education And Experience

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of related experience.
• Master’s degree or PhD with 5+ years of related experience.
• Experience supporting advanced‑node or complex SoC implementation environments.
• Experience with scripting languages such as Tcl or Python.
• Experience or interest in applying AI‑based techniques, automation, or data‑driven approaches to engineering workflows.
• Experience with Synopsys physical design tools; comparable Cadence experience also acceptable.
• Experience partnering across physical design, CAD, STA, DFT, and RTL/design teams.

We recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

Compensation and Benefits

The expected wage range for a new hire into this position is $116,960 to $160,820.

• Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
• This position qualifies for a discretionary performance‑based bonus which is based on personal and company factors.
• This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

Analog Devices is an equal‑opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

For positions requiring access to technical data, Analog Devices may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. Applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.