Physical Design Engineer

Etched.ai, Inc.; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Wellness benefits

Daily lunch and dinner in office

Job summary

Etched.ai, Inc. is seeking a Physical Design Engineer based in Austin, Texas. This role involves owning block-level implementation, driving timing closure, and collaborating with RTL designers to improve design processes. Candidates should have 5-10+ years in physical design, familiarity with advanced process nodes, and tools like Cadence and Synopsys. The position includes medical benefits, wellness programs, and daily office meals, promoting an innovative engineering culture and teamwork across locations.

Qualifications

• 5-10+ years of previous experience with physical design.
• Experience with back-end design and timing closure on advanced process nodes.
• Familiarity with low power design methodologies.

Responsibilities

• Own block-level implementation and verification.
• Collaborate with RTL designers to improve PPA.
• Supervise 3rd party design work.

Skills

Physical Design expertise

Timing closure

Back-end design

Creativity and first principles thinking

Programming in Python

Tools

Cadence (Innovus, Genus)

Synopsys (ICC2, Fusion Compiler)

Sign-off tools (PrimeTime, Tempus, Voltus)

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.

Key Responsibilities

• Deeply understand what is involved in physical design
• Run PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure
• Collaborate with RTL designers and provide Physical Design feedback to improve PPA
• Drive dashboards that show the convergence of projects related to PD
• Optimize tool flows, working with EDA vendors to incorporate the latest features
• Accountable for block level closure
• Supervise the outsourcing of physical design to a 3rd party service

You may be a good fit if you have

• 5-10+ years of previous experience with PD
• Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
• Experience with back-end design and timing closure on advanced process nodes 5nm and below
• Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
• Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
• Deeply creative and able to think from first principles

Strong candidates may also have experience with

• Familiarity with transformer models and machine learning
• Ability to program with Python or another scripting language
• Familiarity with AI tools for programming/coding
• Startup experience or comfort working in fast-paced environments

Benefits

• Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We have a growing presence in Austin and a core team in San Jose (Santana Row), and we greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.