Physical Analysis Engineer

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 150,000 - 225,000; Full time

Job summary

APPLE INC in Cupertino, California is seeking a Hardware / PDN design engineer to debug flow issues and enhance ASIC power delivery networks. You will work across floor planning, clock and power distribution, and run analyses with industry tools to validate chip-level PDN reliability.

The role involves close collaboration with CAD/technology and implementation teams through the full design cycle to drive tape-out sign-off, with an emphasis on static/dynamic power, EM/Noise analyses, scripting

Qualifications

• Bachelor’s degree in Electrical Engineering, Mechatronic Engineering, or related field.
• Experience designing, simulating, and validating large SOC PDN in advanced process nodes.
• Experience with static and power analysis tools like RedHawk or Voltus.

Responsibilities

• Debug flow related issues and enhancements in ASIC PDN design.
• Work with ASIC physical design including floor planning, clock and power distribution.
• Perform analyses with industry tools such as RedHawk, Voltus, ETS, and PT-SI.
• Collaborate with CAD/technology teams for flow bring up and validation; signoff for tapeout.

Skills

Power analysis

PDN design

Static power analysis

Dynamic power analysis

EMIR debugging

Scripting (Python, Tcl, Perl)

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

Ansys RedHawk

Cadence Voltus

Job description

Cupertino, California, United States Hardware

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Debug flow related issues and make enhancements as appropriate. Work with all aspects of ASIC physical design including floor planning, clock and power distribution. Use industry standard tools to perform analyses such as Apache Redhawk, Voltagestorm, ETS, PT-SI. Perform various electrical analyses at the chip level, including but not limited to Static/Dynamic IR, EM, Noise and Signal EM. Work multi-functionally with the CAD/technology teams for flow bring up and validation. Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out. Manage schedules and supporting multi-functional engineering effort. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Bachelor’s degree or foreign equivalent in Electrical Engineering, Mechatronic Engineering, or related field.
• Experience and/or education includes the following:
• Designing, simulating, and validating large SOC PDN (power grid network) with complex structure in the advance technology process node.
• Performing static and power analysis to signoff on the power grid using tools like Ansys RedHawk, or Cadence Voltus.
• Utilizing problem-solving skills, with the ability to debug complex EMIR violations and propose appropriate and effective design fixes.
• Conducting static and dynamic power analysis, analyzing and verifying low power techniques such as power gating, clock gating, to meet project power/IR budgets.
• Performing chip-package co-analysis to identify PDN weakness, such as that caused by dynamic voltage droop, high impedance paths or insufficient decoupling, and assess impact on critical timing paths.
• Creating or automating complex, multi-step engineering workflows, leading to significant reduction in manual efforts and cycle time, using conventional scripting language such as Perl, Tcl, or Python.
• Utilizing post-silicon correlation, collecting and processing DFT scan patterns out of characterization results, and refining pre-silicon EMIR models and signoff methodologies for future projects.

Preferred Qualifications

• N/A

This position is not subject to the application limits.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.