Senior PIC Design Architect, Silicon Photonics

Voya Energy; New York (NY); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Catered lunch daily at HQ

HQ in Midtown Manhattan

Job summary

Voyant Photonics in NYC seeks a Principal PIC Design Engineer to own large-scale silicon photonic chip development from concept to tapeout and characterization.

You will define chip architectures, drive floorplanning and DFM, lead cross-disciplinary teams, and push for high-yield tapeouts while evolving PDKs with foundries.

The role blends device physics, layout, and system-level trade-offs in a fast-paced startup, with hands-on collaboration and visible impact.

Qualifications

• PhD in EE/Photonics with 5+ years in PIC design.
• Experience leading full foundry tapeouts (DRC/LVS) and validation.
• Deep knowledge of photonic device physics, waveguides, and DFM.
• Proficiency with industry tools like Lumerical, Tidy3D, COMSOL, KLayout, and gdsfactory.

Responsibilities

• Lead system-level architecture for large-scale PICs with hundreds to thousands of devices.
• Define chip-level optical architectures, link budgets, and trade-offs across loss, crosstalk, bandwidth, and thermal management.
• Drive integration, floorplanning, optical routing, and high-yield tapeout strategies.
• Contribute to photonic component library development.
• Serve as top-level tapeout owner (DRC/LVS) and foundry coordination.
• Provide technical leadership across multidisciplinary teams (packaging, EIC, systems, software).
• Guide wafer- and chip-level characterization strategies to verify performance and drive design updates.
• Maintain relationships with foundry partners to evaluate next-gen PDks and platforms.

Skills

Silicon photonics

Layout/floorplanning

Top-level design

Team leadership

Python/MATLAB data analysis

Education

PhD in Electrical Engineering, Photonics, or related field

Tools

Ansys Lumerical

Tidy3D

COMSOL

KLayout

gdsfactory

Job description

Voyant Photonics in NYC seeks a Principal PIC Design Engineer to own large-scale silicon photonic chip development from concept to tapeout and characterization.

You will define chip architectures, drive floorplanning and DFM, lead cross-disciplinary teams, and push for high-yield tapeouts while evolving PDKs with foundries.

The role blends device physics, layout, and system-level trade-offs in a fast-paced startup, with hands-on collaboration and visible impact.