PhD Intern: Analog & Mixed-Signal IC Design

Jobtailor; Santa Clara (CA); On-site; USD 50,000 - 70,000; Part time

Job summary

Jobtailor in Santa Clara, CA invites a PhD student in Electrical Engineering to join our analog/mixed-signal design team. Design, simulate, and verify blocks across the full design flow—from architecture and schematic to silicon bring‑up—in advanced CMOS FinFET processes.

Use Cadence and MATLAB for simulation; collaborate with layout engineers; participate in design reviews; and present results. You will also follow a structured analog design curriculum alongside other PhD interns.

Qualifications

• Enrolled in a Ph.D. program with a focus on analog, mixed-signal, or RF circuit design.
• Hands-on experience designing/simulating analog blocks (PLL, SerDes, ADC/DAC, LDO, high-speed I/O).
• Strong transistor-level design fundamentals for advanced CMOS processes.

Responsibilities

• Design, simulate, and verify analog/mixed-signal blocks across the full design flow.
• Collaborate with layout engineers and iterate based on simulation and silicon feedback.
• Attend design reviews and present research framing and results to engineers.
• Participate in a structured analog design curriculum alongside other Ph.D. intern peers.

Skills

Analog Circuit Design

Mixed-Signal Circuit Design

Transistor-Level Circuit Design

High-Speed I/O Design

PLLs

SerDes Building Blocks

ADCs

DACs

LDOs

Device Physics

Education

Ph.D. in Electrical Engineering

Tools

Cadence

MATLAB

Spectre

Verilog-A

Job description

Jobtailor in Santa Clara, CA invites a PhD student in Electrical Engineering to join our analog/mixed-signal design team. Design, simulate, and verify blocks across the full design flow—from architecture and schematic to silicon bring‑up—in advanced CMOS FinFET processes.

Use Cadence and MATLAB for simulation; collaborate with layout engineers; participate in design reviews; and present results. You will also follow a structured analog design curriculum alongside other PhD interns.