Analog Mixed-Signal Design Intern: Cadence & Verification

Infineon Technologies; El Segundo (CA); On-site; USD 41,000 - 48,000; Full time

Job summary

Infineon Technologies in El Segundo, CA is seeking students or recent graduates for design verification roles focusing on analog and digital IP. You will assist with mixed-signal design verification using Cadence tools, develop testbenches, and perform silicon evaluation.

The role emphasizes SystemVerilog/UVM, lab experience with oscilloscopes and DMMs, and scripting in Python/Unix. Collaboration with IC teams is essential for next-generation IP development.

Qualifications

• Currently enrolled in or recently graduated from a Bachelor's or Master's program in Electrical Engineering or a closely related field.
• Hands-on Cadence tools experience for schematic creation, netlist generation, and simulation.
• Familiarity with SystemVerilog and UVM for constrained random testbench development.
• Experience with lab test equipment like oscilloscopes and digital multimeters for hardware bring-up and IC characterization.
• Python programming and Unix/Linux shell scripting for automation and simulation workflow support.
• Awareness of communication protocols PMBus, I2C, UART, or SPI for testbench and firmware co-verification.
• Strong written and verbal communication for cross-functional teamwork.

Responsibilities

• Design Support: Assist with analog and digital design and verification of mixed-signal IP using the Cadence suite of tools across various SoC scenarios
• Testbench Development: Create mixed-signal testbenches and execute simulations for digital multiphase buck controllers, integrated power stages, and voltage regulator designs
• Functional Verification: Perform functional verification of power management circuits including digital multiphase buck controllers and integrated power stages
• Silicon Evaluation: Conduct bench-level silicon evaluation to characterize IC performance, document results, and prepare structured validation reports
• Constrained Random Verification: Develop scalable and reusable constrained random testbenches using SystemVerilog and UVM object-oriented methodologies
• Cross-Functional Collaboration: Partner with analog and digital IC design experts and cross-functional teams to improve unit architecture performance and next-generation IP development
• Skill Development: Build analog and mixed-signal design competencies by actively contributing to next-generation IP and exploring best-in-class product design solutions

Skills

Cadence proficiency

SystemVerilog

UVM

Lab experience

Python

Unix/Linux shell

Hardware protocols

Collaboration

Education

Electrical Engineering degree

Tools

Cadence tools

Job description

Infineon Technologies in El Segundo, CA is seeking students or recent graduates for design verification roles focusing on analog and digital IP. You will assist with mixed-signal design verification using Cadence tools, develop testbenches, and perform silicon evaluation.

The role emphasizes SystemVerilog/UVM, lab experience with oscilloscopes and DMMs, and scripting in Python/Unix. Collaboration with IC teams is essential for next-generation IP development.