Analog/Mixed-Signal Design Intern (Cadence)

Infineon Technologies AG; El Segundo (CA); On-site; USD 41,000 - 48,000; Part time

Job summary

Infineon Technologies is seeking a student/intern to assist with analog and digital design verification of mixed-signal IP across SoC scenarios. You will design and verify using Cadence tools and contribute to testbench development and silicon evaluation.

The role emphasizes SystemVerilog/UVM-based constrained random verification, lab experimentation with test equipment, and collaboration with cross-functional IC design teams to advance next-generation IP.

Qualifications

• Enrolled in or recently graduated from a Bachelors or Masters in Electrical Engineering.
• Hands-on Cadence experience for schematic, netlist, and simulation in analog/mixed-signal env.
• Familiar with SystemVerilog and UVM for constrained random testbenches.
• Lab exposure with oscilloscopes and DMMs for hardware bring-up and IC characterization.

Responsibilities

• Assist with analog and digital design and verification of mixed-signal IP using Cadence tools.
• Develop mixed-signal testbenches and run simulations for power management circuits.
• Perform functional verification of power management blocks including buck controllers.
• Conduct bench-level silicon evaluation and document validation results.
• Develop scalable constrained random testbenches using SystemVerilog and UVM.

Skills

Cadence Proficiency

SystemVerilog

UVM

Python

Lab Measurement

Unix/Linux

I2C/UART/SPI

Education

Bachelor's or Master's in Electrical Engineering

Tools

Oscilloscope

Multimeter

Job description

Infineon Technologies is seeking a student/intern to assist with analog and digital design verification of mixed-signal IP across SoC scenarios. You will design and verify using Cadence tools and contribute to testbench development and silicon evaluation.

The role emphasizes SystemVerilog/UVM-based constrained random verification, lab experimentation with test equipment, and collaboration with cross-functional IC design teams to advance next-generation IP.