PD Intern

The Consensus; San Jose (CA); On-site; USD 34,440 - 55,104; Full time

Benefits offered by this job

12-week paid internship

Housing support for relocation

Daily lunch and dinner in office

Direct mentorship

Work on important AI problems

Job summary

Etched in San Jose is offering a Physical Design internship focused on realizing front-end designs in silicon and improving iteration speed to final signoff.

Interns will help develop and run physical design flows, synthesize blocks, and advise RTL design choices. We seek Fall ’26, Spring ’27, and Summer ’27 interns who are pursuing advanced EE/CE degrees and eager to learn.

Qualifications

• Progress toward a Bachelor’s, Master’s, or PhD in electrical/computer engineering or related field.
• Familiarity with high-speed digital logic.
• Exposure to ASIC or SoC design concepts.
• Familiarity with SystemVerilog, UVM, or Python.
• Familiarity with verification work and writing test benches.
• Familiarity with physical design flows and tooling.
• Able to learn quickly about transformers and other aspects of modern AI.

Responsibilities

• Realize front-end designs in silicon.
• Develop and run Physical Design flows to synthesize blocks.
• Assist RTL design decisions and provide feedback on PD decisions.
• Fall ’26, Spring ’27, and Summer ’27 internship terms.

Skills

High-speed logic

ASIC/SoC concepts

SystemVerilog/UVM/Python

Test benches

Physical design flows

Learning transformers/AI

Education

Bachelor's/Master/PhD in EE/CE

Tools

SystemVerilog

UVM

Python

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

• Familiarity with modern ML and LLM model architectures
• Familiarity with numerical representations and functions (RTL)
• Familiarity with clocking and reset schemes (RTL/PD)
• UVM or formal verification experience (DV)
• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12-week paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our officeBased at our office in San Jose, CA
• Direct mentorship from industry leaders and world-class engineers
• Opportunity to work on one of the most important problems of our time

For any questions, contact [e-mail]

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.