Package Design Engineer

Broadcom; United States; On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Dental insurance

Vision insurance

401(k)

Paid time off

Remote work options

Equity / stock options

Performance bonus

Job summary

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages used in high-speed SerDes and AI-ready ASICs. You will join a worldwide R&D team and lead design efforts from concept through layout, ensuring signal integrity, power integrity, and reliable manufacturability.

The role requires on-site presence at the Broadcom office, a strong background in high-speed packaging, and collaboration with internal and external teams across time zones.

Qualifications

• BSEE or similar field with 8+ years in flip-chip-BGA package design including high-speed SerDes.
• MSEE or similar field with 6+ years of work experience.
• Knowledge of package-level SI/PI to apply to designs.
• Cadence APD Allegro experience preferred; equivalent tool OK.
• Cooperate with global teams across time zones; self-motivated and organized.
• Experience with design-automation coding (Cadence SKILL) is a plus.

Responsibilities

• Overall design responsibility for ASIC package designs, including SI, PI, manufacturability, reliability, and thermal, with our package engineering team.
• Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across 2+ projects simultaneously.
• Project management and customer interface for your design projects.
• Contribute to efficiency improvements for the design team through process development, automation, and documentation.
• Physical design (layout) is a foundational responsibility in this role.

Skills

Signal integrity

Power integrity

Self-management

Team collaboration

Design automation coding

Education

BSEE or equivalent

MSEE or equivalent

Tools

Cadence APD Allegro

Cadence SKILL

Job description

• Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across 2+ projects simultaneously
• Project management and customer interface for your design projects
• Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.
• Physical design (layout) is a foundational responsibility in this role
• EDUCATION/EXPERIENCE & REQUIREMENTS:
• BSEE or similar field and 8+ years' experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years' work experience
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
• Self-management and organization skills
• Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest
• OTHER REQUIREMENTS
• This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position.
• Compensation and Benefits
• The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

• Dental insurance
• Vision insurance
• 401(k)
• Paid time off
• Remote work options
• Equity / stock options
• Performance bonus

Additional Information

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.

Your Match

How well this role fits your profile.

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Filings 3,503

Approved 84.8%

Avg wage $134K

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