Principal Optical Packaging Engineer 3D/2.5D

Astera Labs; San Jose (CA); On-site; USD 205,000 - 260,000; Full time

Job summary

Astera Labs seeks a Principal Advanced Packaging Engineer to lead R&D for next‑generation packaging technologies for optical chips. This senior IC packaging role sets technical direction and drives packaging development for NPO and CPO products.

The position focuses on 2.1D/2.5D/3D integration, wafer-, panel-, and die-level packaging flows, and close collaboration with OSATs and material suppliers to deliver reliable, scalable solutions.

Qualifications

• 8+ years of experience in semiconductor or advanced packaging engineering.
• Expertise in advanced packaging processes including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL and overmold across wafer-, panel-, and die-level flows.
• Experience with silicon photonics chip packaging and EIC/PIC integration.
• Hands-on experience with advanced packaging materials (underfill, molding compounds, dielectrics, adhesives, optical-grade encapsulants).
• Proven track record of equipment and process qualification with OSAT or tool suppliers.
• Experience with PDK development and packaging design rule authoring.
• Strong foundation in yield analysis, reliability characterization, and CpK/SPC.

Responsibilities

• Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
• Define and optimize wafer-level, panel-level, or die-level packaging process flows.
• Drive EIC-to-PIC integration and broader optical device integration efforts.
• Select and qualify packaging materials for advanced packaging.
• Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
• Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.
• Develop and maintain packaging PDKs and design rules for NPO and CPO products.

Skills

2.5D/3D integration

Flip-chip

Hybrid bonding

Cu pillar

TSV

RDL

Overmold

EIC/PIC integration

OSAT collaboration

PDK development

Yield analysis

Cpk/SPC methodologies

Education

B.S./M.S./Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering

Job description

Astera Labs seeks a Principal Advanced Packaging Engineer to lead R&D for next‑generation packaging technologies for optical chips. This senior IC packaging role sets technical direction and drives packaging development for NPO and CPO products.

The position focuses on 2.1D/2.5D/3D integration, wafer-, panel-, and die-level packaging flows, and close collaboration with OSATs and material suppliers to deliver reliable, scalable solutions.