Onsite Senior ASIC Validation Engineer - San Jose, Python/C++

020 Cisco Systems, Inc.; San Jose (CA); Presencial; USD 168.000 - 245.000; Jornada completa

Descripción de la vacante

Cisco Systems, Inc. is seeking a versatile Senior Hardware Engineer for our Silicon One team in San Jose.

You will participate across pre- and post-silicon validation, bring-up, manufacturing support, and reliability improvements to high-performance ASICs. The role requires deep experience in post-silicon validation, power integrity, and high-speed interfaces, with strong Python/C++ software skills for observability tools.

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience, or Master's with 3+ years, or PhD with 1+ year.
• Experience in electrical post-silicon validation (Vmin, leakage, PVT characterization, etc.).
• Software development experience with Python, C++ or similar language.

Responsabilidades

• Lead and participate in failure analysis efforts, determining contributing factors and corrective actions.
• Lead activities aiming at improving product performance, yield, and reliability.
• Define and refine post-silicon validation plans covering functionality, performance characterization, and reliability.
• Capture, analyze, and interpret device performance, waveforms, eye diagrams, jitter, BER, PDN measurements, power supply stability and noise.

Conocimientos

Python

C++

Firmware development

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree in Electrical Engineering or Computer Engineering

PhD in Electrical Engineering or Computer Engineering

Herramientas

Oscilloscopes

VNA

BERT

Logic analyzers

Descripción del empleo

Cisco Systems, Inc. is seeking a versatile Senior Hardware Engineer for our Silicon One team in San Jose.

You will participate across pre- and post-silicon validation, bring-up, manufacturing support, and reliability improvements to high-performance ASICs. The role requires deep experience in post-silicon validation, power integrity, and high-speed interfaces, with strong Python/C++ software skills for observability tools.