NOC & SoC Verification Engineer - UVM/Formal

AMD; San Jose (CA); On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD is seeking a Verification Engineer in San Jose, California, to lead the verification of Network-on-Chip (NOC) IPs and subsystems. This role involves architecting and developing verification environments and ensuring the functional correctness of designs.

The ideal candidate has a strong background in System Verilog, UVM, and ASIC development. Key responsibilities include leading the verification team and designing testbenches for efficient verification.

Qualifications

• Experience with UVM, OVM, VMM, System Verilog, and simulation tools.
• Strong understanding of verification techniques, including assertion and coverage-driven verification.
• Experience in block level NOC verification is a plus.

Responsibilities

• Lead verification of complex digital design blocks.
• Create comprehensive verification test plans with architects.
• Design and architect testbenches in System Verilog and UVM.

Skills

UVM

System Verilog

Verilog test benches

simulation tools

assertion verification

coverage-driven verification

ASIC development

Education

Bachelor's or Master's degree in computer engineering or Electrical Engineering

Job description

AMD is seeking a Verification Engineer in San Jose, California, to lead the verification of Network-on-Chip (NOC) IPs and subsystems. This role involves architecting and developing verification environments and ensuring the functional correctness of designs.

The ideal candidate has a strong background in System Verilog, UVM, and ASIC development. Key responsibilities include leading the verification team and designing testbenches for efficient verification.