NOC Interconnect Architect-Data Center

MediaTek; San Jose (CA); On-site; USD 170,000 - 210,000; Full time

Job summary

A global semiconductor leader is seeking an experienced architect to own the NoC design for data center SoCs. This role requires over 10 years of expertise in SoC architecture and performance modeling, focusing on interconnect fabrics. The ideal candidate will have excellent communication and problem-solving skills. Enjoy a collaborative environment in San Jose, California, or Portland, Oregon, with opportunities for technical leadership.

Qualifications

• 10+ years in SoC architecture, performance analysis, and power optimization.
• Strong foundation in computer architecture and performance analysis.
• Proven experience in designing NoC/interconnect for large-scale SoCs.
• Familiar with AXI/CHI protocols and memory interfaces.

Responsibilities

• Define NoC architecture and topology to meet targets.
• Plan and model traffic and buffers for optimization.
• Lead cross-functional debug and analysis across various domains.
• Evaluate and integrate ARM CMN/CoreLink and Arteris FlexNoC IP.
• Build performance models and map to RTL and silicon.
• Drive PPA tradeoffs; collaborate on floorplan-aware partitioning.
• Define RAS features and safety mechanisms; contribute to safety cases.
• Lead cross-functional debugging and root-cause analysis; deliver fixes.
• Document specs and design guidelines; review with stakeholders.
• Mentor engineers across interconnect domain.

Skills

SoC architecture

Performance modeling

Interconnect fabrics

Problem-solving

Communication

ARM CMN/CoreLink familiarity

Arteris FlexNoC familiarity

AXI/CHI knowledge

Communication & leadership

Debugging/root-cause analysis

Tools

SystemC

TLM

Python

ARM CMN/CoreLink

Arteris FlexNoC

Job description

MediaTek’s Data Center team builds high-performance, power‑efficient, and scalable silicon for next‑generation data centers. We bring together system architects, packaging experts, and SoC designers to deliver reliable solutions that push the boundaries of performance and efficiency.

About the Role

Own the architecture and performance modeling of the NoC for data center‑class SoCs. Collaborate across architecture, RTL, verification, physical design, firmware, and software to plan, evaluate, and deliver competitive interconnect fabrics.

Responsibilities

• Define NoC architecture and topology (e.g., mesh, hierarchical, ring) to meet bandwidth, latency, and scalability targets.
• Plan and model traffic, buffers, virtual channels, arbitration, and QoS to optimize performance and fairness.
• Specify coherency, ordering, and protocol handling for AXI/CHI‑based fabrics; ensure deadlock avoidance and reliability.
• Evaluate and configure industry IP (ARM CMN/CoreLink, Arteris FlexNoC/FlexNoC Gen) and guide customization/integration.
• Build and correlate performance models (SystemC/TLM, vendor tools, Python traffic generators) to RTL and silicon.
• Drive PPA tradeoffs: pipeline stages, link widths, clock/power gating, DVFS; partner with PD on floorplan‑aware partitioning.
• Define and implement RAS features (ECC, parity, retry) and safety mechanisms; contribute to safety cases where applicable.
• Lead cross‑functional debug and root‑cause analysis across RTL/DV/PD/firmware/software; deliver fixes and mitigations.
• Document specifications, microarchitecture, and design guidelines; review and sign‑off with stakeholders.
• Mentor engineers and provide technical leadership across the interconnect domain.

Qualifications

• 10+ years in SoC architecture/RTL/performance analysis/power optimization with a focus on interconnect fabrics.
• Strong foundation in computer architecture, microarchitecture, and performance analysis.
• Proven experience designing and optimizing NoC/interconnect for large‑scale SoCs (data center or similar).
• Hands‑on familiarity with ARM CMN/CoreLink and/or Arteris FlexNoC/FlexNoC Gen.
• Working knowledge of AMBA AXI and CHI protocols; memory interface/protocol exposure is a plus.
• Excellent communication, problem‑solving, root‑cause analysis, and debugging skills.

Preferred Skills

• Experience with server/data center workloads and memory subsystems (DDR5, HBM3/e).
• Knowledge of IO/coherency interfaces (PCIe Gen5/6, CXL.cache/mem) and IOMMU/SMMU.
• Exposure to chiplet/2.5D integration (UCIe) and multi‑die coherency boundaries.
• Familiarity with ISO 26262 (automotive), virtualization, confidential compute, and security/TEE concepts.
• Modeling and analysis tools (SystemC/TLM, gem5, Cadence/Synopsys/Arteris interconnect tools) and Python scripting.
• RTL/SystemVerilog proficiency; understanding of synthesis, timing closure, power analysis, and UPF.

Location: San Jose, California or Portland, Oregon

Equal Opportunity Statement: MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.